@@ -123,7 +123,7 @@ &pcie30phy {
&pcie3x1 {
num-lanes = <1>;
pinctrl-names = "default";
- pinctrl-0 = <&pcie30x1m0_pins>;
+ pinctrl-0 = <&pcie30x1_reset_h>;
reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_minipcie>;
status = "okay";
@@ -148,6 +148,10 @@ pcie30x1_enable_h: pcie30x1-enable-h {
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
+ pcie30x1_reset_h: pcie30x1-reset-h {
+ rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
pcie30x2_reset_h: pcie30x2-reset-h {
rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
};
to avoid conflict with sdmmc_det, change pci3x1 pinctrl-0 name. Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> --- Changes in v2: - new --- arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)