| Message ID | 20241122073006.99309-1-amadeus@jmu.edu.cn (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [1/2] arm64: dts: rockchip: rk3568: add reset-names for combphy | expand |
Am Freitag, 22. November 2024, 08:30:05 CET schrieb Chukun Pan: > The reset-names of combphy are missing, add it. > > Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Fixes: fd3ac6e80497 ("dt-bindings: phy: rockchip: rk3588 has two reset lines") It does looks like, before that patch above, the phy did not use nor require reset-names? No need to resend for this, as I think b4 will just pick up this addition when I grab the series from the list.
Am Freitag, 22. November 2024, 08:56:17 CET schrieb Heiko Stuebner: > No need to resend for this, as I think b4 will just pick up this > addition when I grab the series from the list. Of course, I'll just grab this patch, not the series. The phy driver change will go through the phy tree :-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index ecaefe208e3e..695cccbdab0f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -350,6 +350,7 @@ combphy0: phy@fe820000 { assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; assigned-clock-rates = <100000000>; resets = <&cru SRST_PIPEPHY0>; + reset-names = "phy"; rockchip,pipe-grf = <&pipegrf>; rockchip,pipe-phy-grf = <&pipe_phy_grf0>; #phy-cells = <1>; diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index 62be06f3b863..e55390629114 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -1681,6 +1681,7 @@ combphy1: phy@fe830000 { assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; assigned-clock-rates = <100000000>; resets = <&cru SRST_PIPEPHY1>; + reset-names = "phy"; rockchip,pipe-grf = <&pipegrf>; rockchip,pipe-phy-grf = <&pipe_phy_grf1>; #phy-cells = <1>; @@ -1697,6 +1698,7 @@ combphy2: phy@fe840000 { assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; assigned-clock-rates = <100000000>; resets = <&cru SRST_PIPEPHY2>; + reset-names = "phy"; rockchip,pipe-grf = <&pipegrf>; rockchip,pipe-phy-grf = <&pipe_phy_grf2>; #phy-cells = <1>;
The reset-names of combphy are missing, add it. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 ++ 2 files changed, 3 insertions(+)