@@ -32,26 +32,29 @@
#include "rockchip_drm_drv.h"
-#define RK3288_GRF_SOC_CON6 0x25c
-#define RK3288_EDP_LCDC_SEL BIT(5)
-#define RK3399_GRF_SOC_CON20 0x6250
-#define RK3399_EDP_LCDC_SEL BIT(5)
-
-#define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
-
#define PSR_WAIT_LINE_FLAG_TIMEOUT_MS 100
+#define GRF_REG_FIELD(_reg, _lsb, _msb) { \
+ .reg = _reg, \
+ .lsb = _lsb, \
+ .msb = _msb, \
+ .valid = true, \
+ }
+
+struct rockchip_grf_reg_field {
+ u32 reg;
+ u32 lsb;
+ u32 msb;
+ bool valid;
+};
+
/**
* struct rockchip_dp_chip_data - splite the grf setting of kind of chips
- * @lcdsel_grf_reg: grf register offset of lcdc select
- * @lcdsel_big: reg value of selecting vop big for eDP
- * @lcdsel_lit: reg value of selecting vop little for eDP
+ * @lcdc_sel: grf register field of lcdc_sel
* @chip_type: specific chip type
*/
struct rockchip_dp_chip_data {
- u32 lcdsel_grf_reg;
- u32 lcdsel_big;
- u32 lcdsel_lit;
+ const struct rockchip_grf_reg_field lcdc_sel;
u32 chip_type;
};
@@ -84,6 +87,26 @@ static struct rockchip_dp_device *pdata_encoder_to_dp(struct analogix_dp_plat_da
return container_of(plat_data, struct rockchip_dp_device, plat_data);
}
+static int rockchip_grf_write(struct regmap *grf, u32 reg, u32 mask, u32 val)
+{
+ return regmap_write(grf, reg, (mask << 16) | (val & mask));
+}
+
+static int rockchip_grf_field_write(struct regmap *grf,
+ const struct rockchip_grf_reg_field *field,
+ u32 val)
+{
+ u32 mask;
+
+ if (!field->valid)
+ return 0;
+
+ mask = GENMASK(field->msb, field->lsb);
+ val <<= field->lsb;
+
+ return rockchip_grf_write(grf, field->reg, mask, val);
+}
+
static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
{
reset_control_assert(dp->rst);
@@ -181,7 +204,6 @@ static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder,
struct drm_crtc *crtc;
struct drm_crtc_state *old_crtc_state;
int ret;
- u32 val;
crtc = rockchip_dp_drm_get_new_crtc(encoder, state);
if (!crtc)
@@ -192,24 +214,19 @@ static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder,
if (old_crtc_state && old_crtc_state->self_refresh_active)
return;
- ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
- if (ret < 0)
- return;
-
- if (ret)
- val = dp->data->lcdsel_lit;
- else
- val = dp->data->lcdsel_big;
-
- DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
-
ret = clk_prepare_enable(dp->grfclk);
if (ret < 0) {
DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret);
return;
}
- ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
+ ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
+ if (ret < 0)
+ return;
+
+ DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
+
+ ret = rockchip_grf_field_write(dp->grf, &dp->data->lcdc_sel, ret);
if (ret != 0)
DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret);
@@ -448,16 +465,12 @@ static DEFINE_RUNTIME_DEV_PM_OPS(rockchip_dp_pm_ops, rockchip_dp_suspend,
rockchip_dp_resume, NULL);
static const struct rockchip_dp_chip_data rk3399_edp = {
- .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
- .lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
- .lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
+ .lcdc_sel = GRF_REG_FIELD(0x6250, 5, 5),
.chip_type = RK3399_EDP,
};
static const struct rockchip_dp_chip_data rk3288_dp = {
- .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
- .lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
- .lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
+ .lcdc_sel = GRF_REG_FIELD(0x025c, 5, 5),
.chip_type = RK3288_DP,
};
The formalized struct definition will makes grf field operations more concise and easier to extend. Signed-off-by: Damon Ding <damon.ding@rock-chips.com> --- Changes in v2: - Initialize struct rockchip_dp_chip_data rk3399_edp/rk3288_dp in order of its members --- .../gpu/drm/rockchip/analogix_dp-rockchip.c | 77 +++++++++++-------- 1 file changed, 45 insertions(+), 32 deletions(-)