From patchwork Tue Dec 24 17:06:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 13920382 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B1C63E7718D for ; Tue, 24 Dec 2024 17:24:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=VPQi3pqG/fleZEeKc14j52/ayiu7A2dYc7JsyZjx5UM=; b=sSaNDSnU0Me6xy 4nrn3eecOzKEhnlfyR+Xz1Q2HuGfSHcSeJgkyvIxBhobHIbOLUZWfu04tRqzrdpGcSgsUCR+Df7fS W5h+4QbbECj5+VpxfVCY83H16e0+bl1dC5YbPLHIysFR07gZBwgzi7zWJLwLfm9I6KwqVvESP3QaP HjAsQrfARFdK0Ir56uJmXykmNeiHsr6ejjRMxD1dgJtNtmYCsk2bqOZoIWw0D9qbyQy6YUiGMqqv1 5MT7pUwen1XQkQCyWoArp5uFZrIHe32i3QdZnfANAPdRi24+z0dFvwOybPwoDKMx28m2w3nRyjJc8 qSEEu4z5T+ge6TNxKwsA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tQ8do-0000000CSqG-1rDl; Tue, 24 Dec 2024 17:24:20 +0000 Received: from relay2-d.mail.gandi.net ([217.70.183.194]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tQ8Nb-0000000CMpj-44Wb; Tue, 24 Dec 2024 17:07:37 +0000 Received: by mail.gandi.net (Postfix) with ESMTPSA id 9B5DC40004; Tue, 24 Dec 2024 17:07:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1735060054; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Dlkm5iEGnjrM/0g/DWcfF67rhxN4oprE30zNEwCGgo0=; b=DYX7H+opRaGC9vHfQchChEJj2F8PQOQdXIHRPK9bAOM+u/ERMSIVBuyKyi7AWeAjlJ7rHn kdRcyZ2B52m5tEQnLPgXhTDFxP+sfKXOUkSSpBYnBaYf5N2R0ppYswTQtcAkzqiYyj8Kwf ycDSoKLOuZ7fwI4eCn351YiEe4+b/unBiog0OZhgh6EnsqB0OrZdNP4XSm1FWprx+uGIVJ m/49JVxPD0jC1QD1GS4mbPFJLGxeYq+sMoO8pyIZWDRpb/76W2GKA6X/KMj2pVMXHRvB3n e7W/cA4MNxJvBa0gXhGmTTRntEE2hjbM6aZiLYfdAz08IAc6CtzcEPLRKpZJeQ== From: Miquel Raynal Date: Tue, 24 Dec 2024 18:06:00 +0100 Subject: [PATCH v2 15/27] spi: spi-ti-qspi: Support per spi-mem operation frequency switches MIME-Version: 1.0 Message-Id: <20241224-winbond-6-11-rc1-quad-support-v2-15-ad218dbc406f@bootlin.com> References: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> In-Reply-To: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> To: Mark Brown , Sanjay R Mehta , Serge Semin , Han Xu , Conor Dooley , Daire McNamara , Matthias Brugger , AngeloGioacchino Del Regno , Haibo Chen , Yogesh Gaur , Heiko Stuebner , Michal Simek , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Jacky Huang , Shan-Chun Hung , Chin-Ting Kuo , =?utf-8?q?C=C3=A9dric_Le_Goa?= =?utf-8?q?ter?= , Joel Stanley , Andrew Jeffery , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Maxime Coquelin , Alexandre Torgue , Raju Rangoju Cc: Thomas Petazzoni , Steam Lin , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, linux-aspeed@lists.ozlabs.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com X-Mailer: b4 0.15-dev X-GND-Sasl: miquel.raynal@bootlin.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241224_090736_281385_FF72CFD0 X-CRM114-Status: GOOD ( 12.52 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Every ->exec_op() call correctly configures the spi bus speed to the maximum allowed frequency for the memory using the constant spi default parameter. Since we can now have per-operation constraints, let's use the value that comes from the spi-mem operation structure instead. In case there is no specific limitation for this operation, the default spi device value will be given anyway. The per-operation frequency capability is thus advertised to the spi-mem core. Signed-off-by: Miquel Raynal --- drivers/spi/spi-ti-qspi.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c index 9122350402b5062dfc8bcf70ac47ba51fad64b3e..49516fee74b0f2062c43d714fcb97c7a55580b37 100644 --- a/drivers/spi/spi-ti-qspi.c +++ b/drivers/spi/spi-ti-qspi.c @@ -623,7 +623,7 @@ static int ti_qspi_exec_mem_op(struct spi_mem *mem, mutex_lock(&qspi->list_lock); if (!qspi->mmap_enabled || qspi->current_cs != spi_get_chipselect(mem->spi, 0)) { - ti_qspi_setup_clk(qspi, mem->spi->max_speed_hz); + ti_qspi_setup_clk(qspi, op->max_freq); ti_qspi_enable_memory_map(mem->spi); } ti_qspi_setup_mmap_read(mem->spi, op->cmd.opcode, op->data.buswidth, @@ -658,6 +658,10 @@ static const struct spi_controller_mem_ops ti_qspi_mem_ops = { .adjust_op_size = ti_qspi_adjust_op_size, }; +static const struct spi_controller_mem_caps ti_qspi_mem_caps = { + .per_op_freq = true, +}; + static int ti_qspi_start_transfer_one(struct spi_controller *host, struct spi_message *m) { @@ -777,6 +781,7 @@ static int ti_qspi_probe(struct platform_device *pdev) host->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | SPI_BPW_MASK(8); host->mem_ops = &ti_qspi_mem_ops; + host->mem_caps = &ti_qspi_mem_caps; if (!of_property_read_u32(np, "num-cs", &num_cs)) host->num_chipselect = num_cs;