@@ -82,14 +82,14 @@
#define ROPLL_SSC_EN BIT(0)
/* CMN_REG(0081) */
#define OVRD_PLL_CD_CLK_EN BIT(8)
-#define PLL_CD_HSCLK_EAST_EN BIT(0)
+#define ANA_PLL_CD_HSCLK_EAST_EN BIT(0)
/* CMN_REG(0086) */
#define PLL_PCG_POSTDIV_SEL_MASK GENMASK(7, 4)
#define PLL_PCG_CLK_SEL_MASK GENMASK(3, 1)
#define PLL_PCG_CLK_EN BIT(0)
/* CMN_REG(0087) */
-#define PLL_FRL_MODE_EN BIT(3)
-#define PLL_TX_HS_CLK_EN BIT(2)
+#define ANA_PLL_FRL_MODE_EN BIT(3)
+#define ANA_PLL_TX_HS_CLK_EN BIT(2)
/* CMN_REG(0089) */
#define LCPLL_ALONE_MODE BIT(1)
/* CMN_REG(0097) */