| Message ID | 20250124064619.13893-3-zhangqing@rock-chips.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | clk: rockchip: Fixed some incorrect commits | expand |
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 7d992c3c01ce..f3ef8cbfbdae 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -852,8 +852,8 @@ <0>, <24000000>, <24000000>, <24000000>, <15000000>, <15000000>, - <300000000>, <100000000>, - <400000000>, <100000000>, + <100000000>, <100000000>, + <100000000>, <100000000>, <50000000>, <100000000>, <100000000>, <100000000>, <50000000>, <50000000>,
This reverts commit 0f2ddb128fa20f8441d903285632f2c69e90fae1. Before changing the PLL frequency, in order to avoid overclocking the child clock, set the child clock to a large div first, and then set the CLK as required after the PLL is set. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)