From patchwork Mon Feb 24 08:13:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damon Ding X-Patchwork-Id: 13987551 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C145AC021B3 for ; Mon, 24 Feb 2025 08:19:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=bBHC/eVXft2hUy300Xh8kwxjdBClBr6eTiQU1B96wdA=; b=mXOvM9RnsyF7Gc le4S1zfgx3PAunO0DY9Uut0R6yParwSNvogWZPDr9dXObRRLJsB+hh3C62aP36nj+y9vUt0ZkO4fc TtGo1dlH/+/UYk9lUSvOnHr3xcLxc0xl5TrLCidCzNBi1C5BS4xDT/wENMxY8moqetB01IvXNIphe zDS3gljJPogiw22x57HJiMNYtmbGNitjtHxaBxwolXGW26Fc7Pvnvqq1oAcuNbt0ZiN7pesC5PluM ohD8yeniYzOJN3HgFfKMIiWjmvuJJTtzEXERAqqYDnYx9sm/ja0XUdlFixFmD+6zdXY+eLPGIDbKE kkgXd3wkZrij4e08Henw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tmTgl-0000000CfAT-1yie; Mon, 24 Feb 2025 08:19:43 +0000 Received: from mail-m19731108.qiye.163.com ([220.197.31.108]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tmTbQ-0000000Ce8k-3Dud; Mon, 24 Feb 2025 08:14:14 +0000 Received: from zyb-HP-ProDesk-680-G2-MT.. (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id bfd287db; Mon, 24 Feb 2025 16:14:07 +0800 (GMT+08:00) From: Damon Ding To: heiko@sntech.de Subject: [PATCH v7 06/15] drm/bridge: analogix_dp: Add support for phy configuration. Date: Mon, 24 Feb 2025 16:13:16 +0800 Message-Id: <20250224081325.96724-7-damon.ding@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250224081325.96724-1-damon.ding@rock-chips.com> References: <20250224081325.96724-1-damon.ding@rock-chips.com> MIME-Version: 1.0 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQh4dHlYdTB4eHR8fTB1OTx5WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSEpPSE xVSktLVUpCS0tZBg++ X-HM-Tid: 0a953705470503a3kunmbfd287db X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Mhg6Sww*FjIcMxMzNj0OES0Y Ej4wFDhVSlVKTE9LSENPQ09CTUJKVTMWGhIXVR8aFhQVVR8SFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFPQ0lJNwY+ DKIM-Signature: a=rsa-sha256; b=XtaC5efGs1rZ+8bQ8zfqofxx4Kc/SjV8UtvJeOpH8oWYwAy8ytqBwSnvrsyaYQks/YS1du3zJ2dtSt+SzBL+VEiLFjM4IxEaK+rwal2MyJtV9XZ7c3hqfalhNB2VuKLkhfQFOY98hQpj+vqhFKhVTqkecpsW4EAiLfmRvg6vd6o=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=kcC5s+lcqHFJtOjydPsWaNOe3ZEm67cMW9OGCW6oq2k=; h=date:mime-version:subject:message-id:from; X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250224_001412_977376_64810F38 X-CRM114-Status: GOOD ( 10.86 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dianders@chromium.org, dri-devel@lists.freedesktop.org, hjc@rock-chips.com, Laurent.pinchart@ideasonboard.com, andrzej.hajda@intel.com, robh@kernel.org, rfoss@kernel.org, sebastian.reichel@collabora.com, jernej.skrabec@gmail.com, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, conor+dt@kernel.org, jonas@kwiboo.se, dmitry.baryshkov@linaro.org, Damon Ding , linux-arm-kernel@lists.infradead.org, neil.armstrong@linaro.org, linux-kernel@vger.kernel.org, boris.brezillon@collabora.com, andy.yan@rock-chips.com, krzk+dt@kernel.org, l.stach@pengutronix.de Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Add support to configurate link rate, lane count, voltage swing and pre-emphasis with phy_configure(). It is helpful in application scenarios where analogix controller is mixed with the phy of other vendors. Signed-off-by: Damon Ding Reviewed-by: Dmitry Baryshkov --- Changes in v2: - remove needless assignments for phy_configure() - remove unnecessary changes for phy_power_on()/phy_power_off() Changes in v4: - remove unnecessary &phy_configure_opts_dp.lanes assignments in analogix_dp_set_link_bandwidth() - remove needless &phy_configure_opts_dp.lanes and &phy_configure_opts_dp.link_rate assignments in analogix_dp_set_lane_link_training() Changes in v5: - include for dev_err() - use drm_err() instead of dev_err() Changes in v6: - Pass 'dp' in drm_...() rather than 'dp->drm_dev' Changes in v7: - For the new error logs, use dev_err() as with the other error logs --- .../drm/bridge/analogix/analogix_dp_core.c | 1 + .../gpu/drm/bridge/analogix/analogix_dp_reg.c | 52 +++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index 174e7011bba9..2c94f77c1d4c 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -1683,6 +1683,7 @@ int analogix_dp_resume(struct analogix_dp_device *dp) if (dp->plat_data->power_on) dp->plat_data->power_on(dp->plat_data); + phy_set_mode(dp->phy, PHY_MODE_DP); phy_power_on(dp->phy); analogix_dp_init_dp(dp); diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c index 3afc73c858c4..38fd8d5014d2 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c @@ -11,6 +11,7 @@ #include #include #include +#include #include @@ -513,10 +514,24 @@ void analogix_dp_enable_sw_function(struct analogix_dp_device *dp) void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype) { u32 reg; + int ret; reg = bwtype; if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62)) writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET); + + if (dp->phy) { + union phy_configure_opts phy_cfg = {0}; + + phy_cfg.dp.link_rate = + drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100; + phy_cfg.dp.set_rate = true; + ret = phy_configure(dp->phy, &phy_cfg); + if (ret && ret != -EOPNOTSUPP) { + dev_err(dp->dev, "%s: phy_configure() failed: %d\n", __func__, ret); + return; + } + } } void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype) @@ -530,9 +545,22 @@ void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype) void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count) { u32 reg; + int ret; reg = count; writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET); + + if (dp->phy) { + union phy_configure_opts phy_cfg = {0}; + + phy_cfg.dp.lanes = dp->link_train.lane_count; + phy_cfg.dp.set_lanes = true; + ret = phy_configure(dp->phy, &phy_cfg); + if (ret && ret != -EOPNOTSUPP) { + dev_err(dp->dev, "%s: phy_configure() failed: %d\n", __func__, ret); + return; + } + } } void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count) @@ -546,10 +574,34 @@ void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count) void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp) { u8 lane; + int ret; for (lane = 0; lane < dp->link_train.lane_count; lane++) writel(dp->link_train.training_lane[lane], dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane); + + if (dp->phy) { + union phy_configure_opts phy_cfg = {0}; + + for (lane = 0; lane < dp->link_train.lane_count; lane++) { + u8 training_lane = dp->link_train.training_lane[lane]; + u8 vs, pe; + + vs = (training_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >> + DP_TRAIN_VOLTAGE_SWING_SHIFT; + pe = (training_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >> + DP_TRAIN_PRE_EMPHASIS_SHIFT; + phy_cfg.dp.voltage[lane] = vs; + phy_cfg.dp.pre[lane] = pe; + } + + phy_cfg.dp.set_voltages = true; + ret = phy_configure(dp->phy, &phy_cfg); + if (ret && ret != -EOPNOTSUPP) { + dev_err(dp->dev, "%s: phy_configure() failed: %d\n", __func__, ret); + return; + } + } } u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane)