From patchwork Tue Feb 25 10:26:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 13989792 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EAF71C021B2 for ; Tue, 25 Feb 2025 10:59:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=Uc3BVU5fZU1deO0FUF0PMFle1YlxMhSbKB7OR6Vtunc=; b=pnvFiYFwcOJYuQ e2ct9KBYpmZSZdHkKNd/6yiI1/rR1YuWqy/FTsO8+rfWcTNCLfYFikszvNjsyQz/1FV3wOnESBHVI 5y9etAFcUV76c28UA1vuLQo61vgZkZRcDEG/mxQfAsNfSiiodieIcWvQy1O8HkANzBnpPPuKZRy5f +w+1/4H81PiqtstDyi7hY93hsKZEzGgRpEE4rq2nV6V/OlyOBYZILLdmddcfaHgzFT085Izzv5OKY gfRqg9dcjKiELcL95noDoBA8fq9Svr+MUkS/ZrmQnGN2vKuVIKa1Z9mViM0CX9KOPIKgMJV0vcRQ7 qJ9JIMsrcL2RySCt3cjQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tmseh-0000000Gvke-22RE; Tue, 25 Feb 2025 10:59:15 +0000 Received: from mail-m3277.qiye.163.com ([220.197.32.77]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tms8q-0000000Gow6-2m2w; Tue, 25 Feb 2025 10:26:22 +0000 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id c22892ce; Tue, 25 Feb 2025 18:26:14 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , Sebastian Reichel , Simon Xue , Conor Dooley , Rob Herring , Bjorn Helgaas , linux-pci@vger.kernel.org, =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , devicetree@vger.kernel.org, Lorenzo Pieralisi , Shawn Lin , Manivannan Sadhasivam , linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 1/2] dt-bindings: PCI: dw: rockchip: Add rk3576 support Date: Tue, 25 Feb 2025 18:26:10 +0800 Message-Id: <20250225102611.2096462-1-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQkseQ1YfSB0aTEwYGUJJSBlWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a953ca4987e03afkunmc22892ce X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6MhA6HBw6GDIPFRYcSDkhMxQM ARcwCwpVSlVKTE9LT0xCSkxNSEhNVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFPSEpCNwY+ DKIM-Signature: a=rsa-sha256; b=R3BMLr4VE9NCGf8G4KX+2yLPIsbV569yp/uPk999vqXfs7FFoJL7emRzj64MIQndiq3cBm9P2mt1N8kDy1TPipD1VcFQZzfMPXfVONnsMcpgaFBn9rM6nXgG/5lLBqQSanojrWWu6DtbmY4QSiDKSWW/wlwUgo3s3cTNL3PbEcc=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=HxawArc165Ay2TKvOqn7tpKGAFxaS9bJbDWsvB3viO8=; h=date:mime-version:subject:message-id:from; X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250225_022621_227009_C111CACD X-CRM114-Status: GOOD ( 11.82 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org rk3576 is using DWC PCIe controller, with msi interrupt directly to GIC instead of using GIC ITS, so - no ITS support is required and the 'msi-map' is not required, - a new 'msi' interrupt is needed. Signed-off-by: Kever Yang Signed-off-by: Sebastian Reichel Reviewed-by: Rob Herring (Arm) --- Changes in v7: - Move the rk3576 device specific schema out of common.yaml Changes in v6: - Fix make dt_binding_check and make CHECK_DTBS=y Changes in v5: - Add constraints per device for interrupt-names due to the interrupt is different from rk3588. Changes in v4: - Fix wrong indentation in dt_binding_check report by Rob Changes in v3: - Fix dtb check broken on rk3588 - Update commit message Changes in v2: - remove required 'msi-map' - add interrupt name 'msi' .../bindings/pci/rockchip-dw-pcie-common.yaml | 10 +++- .../bindings/pci/rockchip-dw-pcie.yaml | 55 +++++++++++++++++-- 2 files changed, 57 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml index cc9adfc7611c..2150bd8b5fc2 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml @@ -65,7 +65,11 @@ properties: tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, nf_err_rx, f_err_rx, radm_qoverflow - description: - eDMA write channel 0 interrupt + If the matching interrupt name is "msi", then this is the combinded + MSI line interrupt, which is to support MSI interrupts output to GIC + controller via GIC SPI interrupt instead of GIC its interrupt. + If the matching interrupt name is "dma0", then this is the eDMA write + channel 0 interrupt. - description: eDMA write channel 1 interrupt - description: @@ -81,7 +85,9 @@ properties: - const: msg - const: legacy - const: err - - const: dma0 + - enum: + - msi + - dma0 - const: dma1 - const: dma2 - const: dma3 diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 550d8a684af3..4764a0173ae4 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -16,16 +16,13 @@ description: |+ PCIe IP and thus inherits all the common properties defined in snps,dw-pcie.yaml. -allOf: - - $ref: /schemas/pci/snps,dw-pcie.yaml# - - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml# - properties: compatible: oneOf: - const: rockchip,rk3568-pcie - items: - enum: + - rockchip,rk3576-pcie - rockchip,rk3588-pcie - const: rockchip,rk3568-pcie @@ -71,8 +68,54 @@ properties: vpcie3v3-supply: true -required: - - msi-map +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml# + - if: + not: + properties: + compatible: + contains: + const: rockchip,rk3576-pcie + then: + required: + - msi-map + + - if: + properties: + compatible: + contains: + const: rockchip,rk3576-pcie + then: + properties: + interrupts: + minItems: 6 + maxItems: 6 + interrupt-names: + items: + - const: sys + - const: pmc + - const: msg + - const: legacy + - const: err + - const: msi + else: + properties: + interrupts: + minItems: 5 + interrupt-names: + minItems: 5 + items: + - const: sys + - const: pmc + - const: msg + - const: legacy + - const: err + - const: dma0 + - const: dma1 + - const: dma2 + - const: dma3 + unevaluatedProperties: false