From patchwork Fri Feb 28 20:06:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Frattaroli X-Patchwork-Id: 13997056 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ADB03C282C6 for ; Fri, 28 Feb 2025 20:19:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:To:In-Reply-To:References:Message-Id: MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=otGWfy/40OkkGFYtkCRTBi6hKyejL+in24MwpS6TLjo=; b=vTcbekifr1nzuh A+tOqY0JZYHRR7jqQocozT3aFdux1r2OROpCsF7SO7NsiX5tjORF77nzUQekRaATdMmg+932GXgVp bA3VU74Ymmr+n4ClnC6plaoLUsBSkM2lUaDFpTPUvGWESkt9Xj5H5OXBtrzW++WQcpsS0cv9VQYnR SFteErE/PRzgKuRIB7bRGX2dWvW7NTV/3nQifkuNGk2FJdSoHIIDCS1PyheT+17++VCL91wrvXgmz qxquz8Sd8DyNm+/hatoCtGp6rjtUcwtiOIATN4/jNTStUItZ8TXAZqbENLjVxaSkcm48gBRL4OUuq helXN25IZynHTYgZ7BbA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1to6pl-0000000CZGY-0jsR; Fri, 28 Feb 2025 20:19:45 +0000 Received: from sender4-pp-f112.zoho.com ([136.143.188.112]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1to6e8-0000000CVJE-1bLm; Fri, 28 Feb 2025 20:07:45 +0000 ARC-Seal: i=1; a=rsa-sha256; t=1740773252; cv=none; d=zohomail.com; s=zohoarc; b=XMkauax2Bi01wT1wkLHpHst5H/+XTJw8Ll6GTP7SM/u9+Fy+OU7GIAIxlKBlylGCJ6Y0aHqbiVvfud/P0x+pv5VvLOe4weYM7jhnH/FF6pHO/xIQ/ef4WhpC7nnsbJlB4CiPQlWKe7t+irVenNSio3JCtFXGFBICME6hWaVSEvc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1740773252; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=hC0j5AIeLbOuxXZpJlCeSQapOYCA4pQ4gSJxZQkp7sM=; b=jR3J6b9i94ElLJQg5rB1CaV+4Jyf5SpcZ8eiL6b4k7fkaBTp79n95HaZif0+226XHhVa64vgcuoBDTMNZ6gEF+RGYY6p6J7yJzE1AWOjmM5zwG+m1s89AJ7kCVT6jO4ZLcGNnR19gVTJzmi1eV3BfIaaJeSOTMTGP+YG/grggzg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1740773252; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=hC0j5AIeLbOuxXZpJlCeSQapOYCA4pQ4gSJxZQkp7sM=; b=FUuhjxCEqmbghbGVj65zz4fG/Jkj5GyYXAKRQxQ6YRYjWAcp4IATDff4C6QLc9h7 E4mArEny0BwZYxGbg3glATqNt5bhyWQ2T7aVz3yWpzW7dlj4CIT1jUscRCpKMCqQfNh fzkrcITXNRMEC0fW28D4eEczp40XVPYEG14sUPgQ= Received: by mx.zohomail.com with SMTPS id 1740773249474827.0097059128609; Fri, 28 Feb 2025 12:07:29 -0800 (PST) From: Nicolas Frattaroli Date: Fri, 28 Feb 2025 21:06:55 +0100 Subject: [PATCH v3 5/6] arm64: dts: rockchip: Add thermal trim OTP and tsadc nodes MIME-Version: 1.0 Message-Id: <20250228-rk3576-tsadc-upstream-v3-5-4bfbb3b699b9@collabora.com> References: <20250228-rk3576-tsadc-upstream-v3-0-4bfbb3b699b9@collabora.com> In-Reply-To: <20250228-rk3576-tsadc-upstream-v3-0-4bfbb3b699b9@collabora.com> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner X-Mailer: b4 0.14.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250228_120744_490366_498AE319 X-CRM114-Status: GOOD ( 10.03 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Sebastian Reichel , linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, kernel@collabora.com, linux-arm-kernel@lists.infradead.org Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Thanks to Heiko's work getting OTP working on the RK3576, we can specify the thermal sensor trim values which are stored there now, and with my driver addition to rockchip_thermal, we can make use of these. Add them to the devicetree for the SoC. Signed-off-by: Nicolas Frattaroli --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 57 ++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 6603f442674c09d017a256bc272e33a2fea7cb8d..1d589a961e7f25d1595fbfa3a19f69e3e8bcb990 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1465,6 +1465,30 @@ gpu_leakage: gpu-leakage@21 { log_leakage: log-leakage@22 { reg = <0x22 0x1>; }; + bigcore_tsadc_trim: bigcore-tsadc-trim@24 { + reg = <0x24 0x2>; + bits = <0 10>; + }; + litcore_tsadc_trim: litcore-tsadc-trim@26 { + reg = <0x26 0x2>; + bits = <0 10>; + }; + ddr_tsadc_trim: ddr-tsadc-trim@28 { + reg = <0x28 0x2>; + bits = <0 10>; + }; + npu_tsadc_trim: npu-tsadc-trim@2a { + reg = <0x2a 0x2>; + bits = <0 10>; + }; + gpu_tsadc_trim: gpu-tsadc-trim@2c { + reg = <0x2c 0x2>; + bits = <0 10>; + }; + soc_tsadc_trim: soc-tsadc-trim@64 { + reg = <0x64 0x2>; + bits = <0 10>; + }; }; gic: interrupt-controller@2a701000 { @@ -1876,6 +1900,39 @@ tsadc: tsadc@2ae70000 { rockchip,hw-tshut-temp = <120000>; rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + #address-cells = <1>; + #size-cells = <0>; + + sensor@0 { + reg = <0>; + nvmem-cells = <&soc_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@1 { + reg = <1>; + nvmem-cells = <&bigcore_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@2 { + reg = <2>; + nvmem-cells = <&litcore_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@3 { + reg = <3>; + nvmem-cells = <&ddr_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@4 { + reg = <4>; + nvmem-cells = <&npu_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@5 { + reg = <5>; + nvmem-cells = <&gpu_tsadc_trim>; + nvmem-cell-names = "trim"; + }; }; i2c9: i2c@2ae80000 {