| Message ID | 20250314-rk3576-sige5-eth-clk-begone-v1-1-2858338fc555@collabora.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: rockchip: remove ethm0_clk0_25m_out from Sige5 gmac0 | expand |
On Fri, 14 Mar 2025 16:35:50 +0100, Nicolas Frattaroli wrote: > The GPIO3 A4 pin on the ArmSoM Sige5 is routed to the 40-pin GPIO > header. This pin can serve a variety of functions, including ones of > questionable use to us on a GPIO header such as the 25MHz clock of the > ethernet controller. > > Unfortunately, this is the precise function that it is being claimed for > by the gmac0 node in the Sige5 board dts, meaning it can't be used for > anything else despite serving no useful function in this role. Since it > goes through a RS0108 bidirectional voltage level translator with a > maximum data rate of 24Mbit/s in push-pull mode and 2Mbit/s data rate in > open-drain mode, it's doubtful as to whether the 25MHz clock signal > would even survive to the actual user-accessible pin it terminates in. > > [...] Applied, thanks! [1/1] arm64: dts: rockchip: remove ethm0_clk0_25m_out from Sige5 gmac0 commit: 73d246b4402c3356f6b3d13665de3a51eea7b555 Actually applied this some days ago, but b4 is of the opinion, I didn't sent out an applied-message yet, so doing that now :-) . Best regards,
diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts index 78798b0722a3f36831b1d2c9f29acb83910631cf..828bde7fab68dc6bcbd13d75c8a72540b3666071 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts @@ -194,8 +194,7 @@ &gmac0 { ð0m0_tx_bus2 ð0m0_rx_bus2 ð0m0_rgmii_clk - ð0m0_rgmii_bus - ðm0_clk0_25m_out>; + ð0m0_rgmii_bus>; phy-handle = <&rgmii_phy0>; status = "okay";
The GPIO3 A4 pin on the ArmSoM Sige5 is routed to the 40-pin GPIO header. This pin can serve a variety of functions, including ones of questionable use to us on a GPIO header such as the 25MHz clock of the ethernet controller. Unfortunately, this is the precise function that it is being claimed for by the gmac0 node in the Sige5 board dts, meaning it can't be used for anything else despite serving no useful function in this role. Since it goes through a RS0108 bidirectional voltage level translator with a maximum data rate of 24Mbit/s in push-pull mode and 2Mbit/s data rate in open-drain mode, it's doubtful as to whether the 25MHz clock signal would even survive to the actual user-accessible pin it terminates in. Remove it to leave the pin for users to play with. It's infinitely more useful as a GPIO or even as a PWM. Fixes: 40f742b07ab2 ("arm64: dts: rockchip: Add rk3576-armsom-sige5 board") Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> --- While working on a PWM driver for RK3576 and needing a PWM pin to test with, I noticed this questionable pinctrl assignment. --- arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) --- base-commit: 40a111d0a777f60b71369d835cfe46308a212235 change-id: 20250314-rk3576-sige5-eth-clk-begone-31d19a7c1e68 Best regards,