From patchwork Mon Mar 17 13:49:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Frattaroli X-Patchwork-Id: 14019291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 03448C35FF9 for ; Mon, 17 Mar 2025 14:08:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:To:In-Reply-To:References:Message-Id: MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=AKDf8a9hkCehp7uHu+z1X/uqpA/9m2Cz++Xh9o6OyW0=; b=iyDp6qJS6swY2/ vebOeLbYK/TD2MOS1GCHntzdXZCtk1UOpfC0qTcltLT0wb3f+Sna4I1KbPTOiDp+hZUHRVwYaalme UEkjcJQTj/bSqQ+7Ztqk5Ef7TocLkacb/FsW1wbZJ9b+LlWM/aSc66a8z+cOUBa1Bhc9LUtnV9qyh VJ0phdeVVE66b8LSSMk72nFYUTlAckelTHm5TqXz0bKUkt6pNKq/1PUaInZu7y3zPZaIVawMrj5xC 74X5Koil0Kad0FD3yvLkqdv77LW+tIXDjCbrTdVOAOtSIBsafvwvNl3Uq0dnaU3xep7QVR+Z0bp6n 69ZBlnjRHFEwXDfuZ+Rw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tuB8p-00000002rC3-1GPm; Mon, 17 Mar 2025 14:08:31 +0000 Received: from sender4-pp-f112.zoho.com ([136.143.188.112]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tuArn-00000002o3f-11Ob; Mon, 17 Mar 2025 13:50:56 +0000 ARC-Seal: i=1; a=rsa-sha256; t=1742219443; cv=none; d=zohomail.com; s=zohoarc; b=GafCc7Fxa1MfqQ0lEIoNsL/wwfdl1CVrTuLWlcGqoOgQ/IX87ZYfIU5BmrOxX0RsbX0UYSecVLEzikctmN6CAyxFstpadnKqtkj2YFvNRPfTTfYniHvbEISCyk2QE9wr0pEtZyDSwwdrqAty49EmfiQ5s50iFhDtqmRSyaj3zcE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742219443; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=nSSLB3r5L5l2WHm3T8V1rB+aRqL74ziqrn6q0GpxVUg=; b=a/Y0at7ri8bNnLKTSGUK29UxEURiMk44rRiPMqV1uPF3DcowRMPPFAU985Hb8sgmYvvtLZDtGQwDePUzQR64N4wnGlIRdUUYcNgNMjbTtJvStKp0j3bEIzIr297yk60cZBVvgesLQojXYbzSvtawgxar0btoSpz0OA97fWEC5JU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1742219443; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=nSSLB3r5L5l2WHm3T8V1rB+aRqL74ziqrn6q0GpxVUg=; b=Qncnz0Zmr0rteXTB+aGTV/Un/ZgMLOFdqq+JAGo4HZqWQBjgg2Wous5e2MomILcg vOXK3u0mVtfOX6LJ0qKy+RT4610lK1JrfZfS8HA76T2d0kVKRfssrkKlllSbQYNXCLZ CTCnP2JFZOXxq83S0hgJCb6I+rYO+hptyw2Y5Dxk= Received: by mx.zohomail.com with SMTPS id 1742219442290840.7508153932768; Mon, 17 Mar 2025 06:50:42 -0700 (PDT) From: Nicolas Frattaroli Date: Mon, 17 Mar 2025 14:49:31 +0100 Subject: [PATCH v4 6/7] arm64: dts: rockchip: Add thermal trim OTP and tsadc nodes MIME-Version: 1.0 Message-Id: <20250317-rk3576-tsadc-upstream-v4-6-c5029ce55d74@collabora.com> References: <20250317-rk3576-tsadc-upstream-v4-0-c5029ce55d74@collabora.com> In-Reply-To: <20250317-rk3576-tsadc-upstream-v4-0-c5029ce55d74@collabora.com> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Jonas Karlman X-Mailer: b4 0.14.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250317_065055_333988_CE46D156 X-CRM114-Status: UNSURE ( 9.89 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Sebastian Reichel , linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, kernel@collabora.com, linux-arm-kernel@lists.infradead.org Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Thanks to Heiko's work getting OTP working on the RK3576, we can specify the thermal sensor trim values which are stored there now, and with my driver addition to rockchip_thermal, we can make use of these. Add them to the devicetree for the SoC. Signed-off-by: Nicolas Frattaroli --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 57 ++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 250dca23ff4fc1ab3bd47366829c5dd1738057fe..6adfa0bfbe9e7ee03f4f516ff91b5c67e5c8346d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1600,6 +1600,30 @@ gpu_leakage: gpu-leakage@21 { log_leakage: log-leakage@22 { reg = <0x22 0x1>; }; + bigcore_tsadc_trim: bigcore-tsadc-trim@24 { + reg = <0x24 0x2>; + bits = <0 10>; + }; + litcore_tsadc_trim: litcore-tsadc-trim@26 { + reg = <0x26 0x2>; + bits = <0 10>; + }; + ddr_tsadc_trim: ddr-tsadc-trim@28 { + reg = <0x28 0x2>; + bits = <0 10>; + }; + npu_tsadc_trim: npu-tsadc-trim@2a { + reg = <0x2a 0x2>; + bits = <0 10>; + }; + gpu_tsadc_trim: gpu-tsadc-trim@2c { + reg = <0x2c 0x2>; + bits = <0 10>; + }; + soc_tsadc_trim: soc-tsadc-trim@64 { + reg = <0x64 0x2>; + bits = <0 10>; + }; }; gic: interrupt-controller@2a701000 { @@ -2011,6 +2035,39 @@ tsadc: tsadc@2ae70000 { rockchip,hw-tshut-temp = <120000>; rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + #address-cells = <1>; + #size-cells = <0>; + + sensor@0 { + reg = <0>; + nvmem-cells = <&soc_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@1 { + reg = <1>; + nvmem-cells = <&bigcore_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@2 { + reg = <2>; + nvmem-cells = <&litcore_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@3 { + reg = <3>; + nvmem-cells = <&ddr_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@4 { + reg = <4>; + nvmem-cells = <&npu_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@5 { + reg = <5>; + nvmem-cells = <&gpu_tsadc_trim>; + nvmem-cell-names = "trim"; + }; }; i2c9: i2c@2ae80000 {