@@ -57,36 +57,77 @@ cpu0: cpu@0 {
#cooling-cells = <2>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l3_cache>;
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
#cooling-cells = <2>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l3_cache>;
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
#cooling-cells = <2>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l3_cache>;
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
#cooling-cells = <2>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l3_cache>;
};
};
+ /*
+ * There are no private per-core L2 caches, but only the
+ * L3 cache that appears to the CPU cores as L2 caches
+ */
+ l3_cache: l3-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ };
+
cpu0_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;