From patchwork Fri Oct 2 09:19:37 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Heiko_St=C3=BCbner?= X-Patchwork-Id: 7314301 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id BBC519F1D5 for ; Fri, 2 Oct 2015 09:20:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id ACF2020892 for ; Fri, 2 Oct 2015 09:20:12 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8702620891 for ; Fri, 2 Oct 2015 09:20:11 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZhwVd-0002cS-Ls; Fri, 02 Oct 2015 09:20:09 +0000 Received: from gloria.sntech.de ([95.129.55.99]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZhwVa-0001QW-SL; Fri, 02 Oct 2015 09:20:08 +0000 Received: from ip5f5b95ad.dynamic.kabel-deutschland.de ([95.91.149.173] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1ZhwV8-0008Us-6B; Fri, 02 Oct 2015 11:19:38 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Xing Zheng Subject: Re: [PATCH v3 6/8] ARM: rockchip: add support smp for rk3036 Date: Fri, 02 Oct 2015 11:19:37 +0200 Message-ID: <3169044.xzd1xSvYRt@diego> User-Agent: KMail/4.14.10 (Linux/4.1.0-2-amd64; KDE/4.14.10; x86_64; ; ) In-Reply-To: <1443492833-15630-7-git-send-email-zhengxing@rock-chips.com> References: <1443492833-15630-1-git-send-email-zhengxing@rock-chips.com> <1443492833-15630-7-git-send-email-zhengxing@rock-chips.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151002_022007_105847_510FF426 X-CRM114-Status: GOOD ( 30.64 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, Russell King , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi, Am Dienstag, 29. September 2015, 10:13:51 schrieb Xing Zheng: > The rk3036 is dual-core soc, we can use this patch to enable cpu1 > enter boot secondary, and hotplug(online/offline). > > Signed-off-by: Xing Zheng > Reviewed-by: Heiko Stuebner > --- > > Changes in v3: None > > arch/arm/mach-rockchip/platsmp.c | 142 > ++++++++++++++++++++++++++++++++++++++ 1 file changed, 142 insertions(+) > > diff --git a/arch/arm/mach-rockchip/platsmp.c > b/arch/arm/mach-rockchip/platsmp.c index 3e7a4b7..7864bf3 100644 > --- a/arch/arm/mach-rockchip/platsmp.c > +++ b/arch/arm/mach-rockchip/platsmp.c > @@ -34,6 +34,8 @@ > > static void __iomem *scu_base_addr; > static void __iomem *sram_base_addr; > +static void __iomem *cru_base_addr; > + > static int ncores; > > #define PMU_PWRDN_CON 0x08 > @@ -41,6 +43,8 @@ static int ncores; > > #define PMU_PWRDN_SCU 4 > > +#define RK3036_SOFTRST_CON(x) ((x) * 0x4 + 0x110) > + > static struct regmap *pmu; > > static int pmu_power_domain_is_on(int pd) > @@ -350,3 +354,141 @@ static struct smp_operations rockchip_smp_ops > __initdata = { }; > > CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", > &rockchip_smp_ops); + > +/* for RK3036 */ > + > +static int rk3036_set_power_domain(int pd, bool on) > +{ > + struct reset_control *rstc = rockchip_get_core_reset(pd); > + u32 val; > + > + /* there are 2cpus on rk3036 soc, we just need to be care cpu1 */ > + if (pd != 1) > + return 0; > + > + if (IS_ERR(rstc) && read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) { > + pr_err("%s: could not get reset control for core %d\n", > + __func__, pd); > + return PTR_ERR(rstc); > + } > + > + /* > + * We need to soft reset the cpu when we turn off the cpu power domain, > + * or else the active processors might be stalled when the individual > + * processor is powered down. > + */ > + if (!IS_ERR(rstc) && !on) > + reset_control_assert(rstc); > + > + val = (on) ? 0 : 1; > + val = (val << pd) | BIT(pd + 16); > + writel_relaxed(val, cru_base_addr + RK3036_SOFTRST_CON(0)); simply mapping the CRU in some arbitary part and then writing to the raw reset register is just a no-go. Even more, as it also conflicts with the reset-control handling directly above and below. > + > + dsb(); > + > + if (!IS_ERR(rstc)) { > + if (on) > + reset_control_deassert(rstc); > + reset_control_put(rstc); > + } > + > + return 0; > +} In general you are duplicating a lot of code for the simple case of not being able to control the power domains. The following should do the trick as well I'd think and produce a lot less code duplication? [of course adapting the dts slightly for the sram now old name] Heiko -------------- 8< -------------- From 3b3910db3a783f625dcc1f05c547680c61c9c818 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 2 Oct 2015 10:24:08 +0200 Subject: [PATCH] ARM: rockchip: add support smp for rk3036 The dual-core Cortex A7 rk3036 is a bit special in that it does not allow to control the actual powerdomain of the cpu cores, while the rest of the smp-bringup like reset control and entry address handling stays the same. Its bigger sibling, the quad-core rk3128 again allows powerdomain control. So allow that case by introducing a separate smp-enable-method, that simply disables powerdomain handling in the common code. Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/cpus.txt | 1 + arch/arm/mach-rockchip/platsmp.c | 45 +++++++++++++++++++------- 2 files changed, 34 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 91e6e5c..261cc27 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -198,6 +198,7 @@ nodes to be present and contain the properties described below. "qcom,gcc-msm8660" "qcom,kpss-acc-v1" "qcom,kpss-acc-v2" + "rockchip,rk3036-smp" "rockchip,rk3066-smp" "ste,dbx500-smp" diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c index 3e7a4b7..5c138f9 100644 --- a/arch/arm/mach-rockchip/platsmp.c +++ b/arch/arm/mach-rockchip/platsmp.c @@ -42,6 +42,7 @@ static int ncores; #define PMU_PWRDN_SCU 4 static struct regmap *pmu; +static int has_pmu = true; static int pmu_power_domain_is_on(int pd) { @@ -89,20 +90,23 @@ static int pmu_set_power_domain(int pd, bool on) if (!IS_ERR(rstc) && !on) reset_control_assert(rstc); - ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val); - if (ret < 0) { - pr_err("%s: could not update power domain\n", __func__); - return ret; - } - - ret = -1; - while (ret != on) { - ret = pmu_power_domain_is_on(pd); + if (has_pmu) { + ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val); if (ret < 0) { - pr_err("%s: could not read power domain state\n", + pr_err("%s: could not update power domain\n", __func__); return ret; } + + ret = -1; + while (ret != on) { + ret = pmu_power_domain_is_on(pd); + if (ret < 0) { + pr_err("%s: could not read power domain state\n", + __func__); + return ret; + } + } } if (!IS_ERR(rstc)) { @@ -122,7 +126,7 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle) { int ret; - if (!sram_base_addr || !pmu) { + if (!sram_base_addr || (has_pmu && !pmu)) { pr_err("%s: sram or pmu missing for cpu boot\n", __func__); return -ENXIO; } @@ -275,7 +279,7 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus) return; } - if (rockchip_smp_prepare_pmu()) + if (has_pmu && rockchip_smp_prepare_pmu()) return; if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { @@ -318,6 +322,13 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus) pmu_set_power_domain(0 + i, false); } +static void __init rk3036_smp_prepare_cpus(unsigned int max_cpus) +{ + has_pmu = false; + + rockchip_smp_prepare_cpus(max_cpus); +} + #ifdef CONFIG_HOTPLUG_CPU static int rockchip_cpu_kill(unsigned int cpu) { @@ -340,6 +351,15 @@ static void rockchip_cpu_die(unsigned int cpu) } #endif +static struct smp_operations rk3036_smp_ops __initdata = { + .smp_prepare_cpus = rk3036_smp_prepare_cpus, + .smp_boot_secondary = rockchip_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_kill = rockchip_cpu_kill, + .cpu_die = rockchip_cpu_die, +#endif +}; + static struct smp_operations rockchip_smp_ops __initdata = { .smp_prepare_cpus = rockchip_smp_prepare_cpus, .smp_boot_secondary = rockchip_boot_secondary, @@ -349,4 +369,5 @@ static struct smp_operations rockchip_smp_ops __initdata = { #endif }; +CPU_METHOD_OF_DECLARE(rk3036_smp, "rockchip,rk3036-smp", &rk3036_smp_ops); CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);