From patchwork Thu Jul 23 08:29:34 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Heiko_St=C3=BCbner?= X-Patchwork-Id: 6851671 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2EEA59F358 for ; Thu, 23 Jul 2015 08:30:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4C9AD206A4 for ; Thu, 23 Jul 2015 08:30:05 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 21D6320694 for ; Thu, 23 Jul 2015 08:30:04 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZIBtC-0006kg-SP; Thu, 23 Jul 2015 08:30:02 +0000 Received: from gloria.sntech.de ([95.129.55.99]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZIBt9-0006UF-Vu; Thu, 23 Jul 2015 08:30:00 +0000 Received: from [95.91.187.196] (helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1ZIBsl-0007Q5-HE; Thu, 23 Jul 2015 10:29:35 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: linux-rockchip@lists.infradead.org Subject: [PATCH v2 1/2] ARM: rockchip: set correct stabilization thresholds in suspend Date: Thu, 23 Jul 2015 10:29:34 +0200 Message-ID: <4610448.RXXf22Qoxl@diego> User-Agent: KMail/4.14.1 (Linux/3.16.0-4-amd64; KDE/4.14.2; x86_64; ; ) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150723_013000_197251_A0C91F67 X-CRM114-Status: GOOD ( 12.41 ) X-Spam-Score: -3.8 (---) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chris Zhong , dianders@chromium.org, linux-arm-kernel@lists.infradead.org, amstan@chromium.org Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Currently the stabilization thresholds for the oscillator and external pmu are statically set to 30ms based on a 32kHz clock rate. This leaves out the case when we don't switch to the 32kHz clock when only entering the shallow suspend mode where the logic keeps running. So, set the correct threshold after we have determined if we switch to the 32kHz clock or stay with the 24MHz one. Reported-by: Chris Zhong Signed-off-by: Heiko Stuebner --- changes since v1: - 24MHz oriented threshold is only needed in shallow suspend, the deep suspend always switches to 32kHz and only leaves the 24MHz oscillator running if needed for stuff like usb wakeup arch/arm/mach-rockchip/pm.c | 11 ++++++++--- arch/arm/mach-rockchip/pm.h | 4 ---- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c index 892bace..04d3028 100644 --- a/arch/arm/mach-rockchip/pm.c +++ b/arch/arm/mach-rockchip/pm.c @@ -145,6 +145,10 @@ static void rk3288_slp_mode_set(int level) mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) | BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA); + + /* 30ms on a 32kHz clock for osc and pmic stabilization */ + regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, 32 * 30); + regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 32 * 30); } else { /* * arm off, logic normal @@ -152,6 +156,10 @@ static void rk3288_slp_mode_set(int level) * wakeup will be error */ mode_set |= BIT(PMU_CLK_CORE_SRC_GATE_EN); + + /* 30ms on a 24MHz clock for osc and pmic stabilization */ + regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, 24000 * 30); + regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 24000 * 30); } regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, mode_set); @@ -262,9 +270,6 @@ static int rk3288_suspend_init(struct device_node *np) memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume, rk3288_bootram_sz); - regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, OSC_STABL_CNT_THRESH); - regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, PMU_STABL_CNT_THRESH); - return 0; } diff --git a/arch/arm/mach-rockchip/pm.h b/arch/arm/mach-rockchip/pm.h index b6494c2..8a55ee2 100644 --- a/arch/arm/mach-rockchip/pm.h +++ b/arch/arm/mach-rockchip/pm.h @@ -62,10 +62,6 @@ static inline void rockchip_suspend_init(void) /* PMU_WAKEUP_CFG1 bits */ #define PMU_ARMINT_WAKEUP_EN BIT(0) -/* wait 30ms for OSC stable and 30ms for pmic stable */ -#define OSC_STABL_CNT_THRESH (32 * 30) -#define PMU_STABL_CNT_THRESH (32 * 30) - enum rk3288_pwr_mode_con { PMU_PWR_MODE_EN = 0, PMU_CLK_CORE_SRC_GATE_EN,