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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 3piQ96u0s8q68Si3BiArpxM+N+ycoT3hZA3HXblFA6xcegT9bm9toMBv7yb51Z4PCIl7GM0/8kZikAvnPbaQ0rQvyz6CR10Ok3R7sz7+pzMOsJrvQwH8cFi94Jhi4MuZ5OPeEudWU90QiRbfxmJyVQRt+7Q9JHQib1Ja+R32MhYZVfM4GvM9LLlCGhW4H9IsZGfIQVoui2aOIW3IpmDcciYQoEbZf3jC9iO5XT6yxl1Fqbe/trtBoAYNMJuZlkxpUaSQMwrDB6LGeLyuQCe8AHbIqiHa3BXszrOGqJanJ2x9i7W7TKPsAZQiRSGrLaWo8iQI5wBNKPoO8lvBK3tITfydcW76k695IMWzfy8a2u93VuNWOqK92FZqjhVfzTO78tukl4H1liB/W27GYCGgw21l4bi7t1MkznjEv19cprph419fB3oCJPlyV/dN3GfMvGqEiQYMmeUokO0Jvv1wPNK9+a5q/+/ceZXHpwp3/F4cJP3J22V0Df7vL03inIaEy+104Rq5d4t15Uv9FXDKZZHzGU7UXfZs+VG41XFQqJWCJqrM0vZUzKnF3VAZKeasFW9Xx6Afj/Vz3ryWQsw1P74cpcjhpMqc+fUwTQ0grhhDAO2imoeOh4Oa6NORBg63fGcvkDzF5DcaYoSCNrosS1GgiTItj2o0z24SKuuEF/xnhpl2FVS3hVlySwpt19Z9M++CwReHacHnHf+LYjmpllU72GUig/43CCfbZMS7lnxwoIHJxKf1YVg51ZG/OA9ngj//4FUA82EQc9MzecEfwNZ/acAuOBHFLVWRX02eWtVk2QW5B0RjF7nMV9Jb17pwbDjhGbG7xrKQ6mMhMigwDCLQWaw6D3Mn1ULs5+oaEoEyVV+w3RYSDJtplVjUNv0NWuTw4HBn/sR2Dgj8RZqNnu+wur2pzzNjFschxj1YPf5+C2J3mCsXTgnKVJiNhnKZssTGgnFQuvQcXU+Pih3srG0r3iwPUoRun53wUBhmFLobkPaCm6BZjFdbjeMZoorpqhaqygKA2hrYZuh0aAnngYT68udGdfHqnWr8lZOvbHgfOAIsehz6kjhRpNC4CMpeKfsCR8tf08bFBhjUXzDzLwltAiVsqdwChQ3g11gPZlbCkgZ3XWK7CWLSbRpIvnB+0QRzypkO9b5M9AGEvVP35rH2xr0Uwgi99yzb/AyKKSFQY2hRT0Rarckh5ijxtvOypH2r2duedv85u2x3rck6ZOr/98aAxyJNod55A7M2CK4A555OAdaAXxz5TKrdYZCibjX15xBEZalC2MznC+8/giKPPeHJOkHZrmiJD5hwtBkXXDv38n5M8uBNuLz+sky5sPTh0fb2r1JyecSeCOwbSkmNw7QAiVnMGovzhi6/sYfOr9OAjEEl4THj+QsXF5rBGRQH7sOYlsy/cDUiLG3feRWfWGhyGp+JGpARZERouQV9TKe1S4m74FoA7ED5NzgINAI9n2imO2+uAVDp3+mumw95n/cSph+ZBhkyZqJVOF5EDsiWPEe4EMVJk9Ll0GThKsykzdzxxCn2zAmZIdjI95eShjmnrSejL3lyEKgxwBJj1htZhSmCNTagRewYtE7K X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 366b4628-7e43-490f-6a6a-08db55a0a320 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2023 00:01:02.5352 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: NnKD8mry1EG3IuY7OoxHHCddR05IzlElZONQy3WDIOXB2G7dbdsUN2xoI6AVHPr/ X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6634 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230515_170117_183400_B3CEE3BA X-CRM114-Status: GOOD ( 16.98 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Robin was able to check the documentation and what fsl_pamu has historically called detach_dev() is really putting the IOMMU into an IDENTITY mode. Move to the new core support for ARM_DMA_USE_IOMMU by defining ops->identity_domain. This is a ppc driver without any dma_ops, so ensure the identity translation is the default domain. Signed-off-by: Jason Gunthorpe --- drivers/iommu/fsl_pamu_domain.c | 32 +++++++++++++++++++++++++++++--- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/fsl_pamu_domain.c b/drivers/iommu/fsl_pamu_domain.c index bce37229709965..ca4f5ebf028783 100644 --- a/drivers/iommu/fsl_pamu_domain.c +++ b/drivers/iommu/fsl_pamu_domain.c @@ -283,15 +283,21 @@ static int fsl_pamu_attach_device(struct iommu_domain *domain, return ret; } -static void fsl_pamu_set_platform_dma(struct device *dev) +static int fsl_pamu_identity_attach(struct iommu_domain *platform_domain, + struct device *dev) { struct iommu_domain *domain = iommu_get_domain_for_dev(dev); - struct fsl_dma_domain *dma_domain = to_fsl_dma_domain(domain); + struct fsl_dma_domain *dma_domain; const u32 *prop; int len; struct pci_dev *pdev = NULL; struct pci_controller *pci_ctl; + if (domain == platform_domain || !domain) + return 0; + + dma_domain = to_fsl_dma_domain(domain); + /* * Use LIODN of the PCI controller while detaching a * PCI device. @@ -312,8 +318,18 @@ static void fsl_pamu_set_platform_dma(struct device *dev) detach_device(dev, dma_domain); else pr_debug("missing fsl,liodn property at %pOF\n", dev->of_node); + return 0; } +static struct iommu_domain_ops fsl_pamu_identity_ops = { + .attach_dev = fsl_pamu_identity_attach, +}; + +static struct iommu_domain fsl_pamu_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &fsl_pamu_identity_ops, +}; + /* Set the domain stash attribute */ int fsl_pamu_configure_l1_stash(struct iommu_domain *domain, u32 cpu) { @@ -447,12 +463,22 @@ static struct iommu_device *fsl_pamu_probe_device(struct device *dev) return &pamu_iommu; } +static int fsl_pamu_def_domain_type(struct device *dev) +{ + /* + * This platform does not use dma_ops at all so the normally the iommu + * must be in identity mode + */ + return IOMMU_DOMAIN_IDENTITY; +} + static const struct iommu_ops fsl_pamu_ops = { + .identity_domain = &fsl_pamu_identity_domain, + .def_domain_type = &fsl_pamu_def_domain_type, .capable = fsl_pamu_capable, .domain_alloc = fsl_pamu_domain_alloc, .probe_device = fsl_pamu_probe_device, .device_group = fsl_pamu_device_group, - .set_platform_dma_ops = fsl_pamu_set_platform_dma, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = fsl_pamu_attach_device, .iova_to_phys = fsl_pamu_iova_to_phys,