From patchwork Fri Mar 27 11:13:56 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russell King X-Patchwork-Id: 6105571 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 65F6E9F350 for ; Fri, 27 Mar 2015 11:15:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7FEA22041F for ; Fri, 27 Mar 2015 11:15:43 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6A946203B7 for ; Fri, 27 Mar 2015 11:15:42 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YbSEn-00052E-CW; Fri, 27 Mar 2015 11:15:41 +0000 Received: from pandora.arm.linux.org.uk ([2001:4d48:ad52:3201:214:fdff:fe10:1be6]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YbSDd-00036I-Gj for linux-rockchip@lists.infradead.org; Fri, 27 Mar 2015 11:14:30 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=arm.linux.org.uk; s=pandora-2014; h=Date:Sender:Message-Id:Content-Type:Content-Transfer-Encoding:MIME-Version:Subject:Cc:To:From:References:In-Reply-To; bh=RMA8bzSO3i+jYdHqh2FaTxbI0gCs17HByexWEUvVpDU=; b=MIdsAJt6fcJyaza+K1eA3DA71xVlSYkeChoHO1heK9VFbKXem/6BAnN3tbyD4r0nwPQ6Oco770E2s7YpYj2gYC70CYmkeeWmZR07cFM9HI7BzizQ0qKFB2Jtp86nM0rfkjD5RuUml+uHE9u17jJSZa52y2VCZ/lcqxyYhxL3yEs=; Received: from e0022681537dd.dyn.arm.linux.org.uk ([2002:4e20:1eda:1:222:68ff:fe15:37dd]:39382 helo=rmk-PC.arm.linux.org.uk) by pandora.arm.linux.org.uk with esmtpsa (TLSv1:DHE-RSA-AES256-SHA:256) (Exim 4.82_1-5b7a7c0-XX) (envelope-from ) id 1YbSD8-0006Et-O2; Fri, 27 Mar 2015 11:13:58 +0000 Received: from rmk by rmk-PC.arm.linux.org.uk with local (Exim 4.76) (envelope-from ) id 1YbSD6-0007z9-2B; Fri, 27 Mar 2015 11:13:56 +0000 In-Reply-To: <20150327111320.GA4019@n2100.arm.linux.org.uk> References: <20150327111320.GA4019@n2100.arm.linux.org.uk> From: Russell King To: linux-rockchip@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/3] drm: bridge/dw_hdmi: adjust n/cts setting order MIME-Version: 1.0 Content-Disposition: inline Message-Id: Date: Fri, 27 Mar 2015 11:13:56 +0000 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150327_041430_030779_86BE6002 X-CRM114-Status: UNSURE ( 9.96 ) X-CRM114-Notice: Please train this message. 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Yakir Yang says: For Designerware HDMI, the following write sequence is recommended: 1. aud_n3 (set bit ncts_atomic_write if desired) 2. aud_cts3 (set CTS_manual and CTS value if desired/enabled) 3. aud_cts2 (required in CTS_manual) 4. aud_cts1 (required in CTS_manual) 5. aud_n3 (bit ncts_atomic_write with same value as in step 1.) 6. aud_n2 7. aud_n1 However, avoid the ncts_atomic_write_bit and CTS_manual settings in this patch, both of which are marked reserved in the iMX6 documentation. All iMX6 code in the wild seems to want CTS_manual cleared. Having requested clarification from FSL, it appears that neither of these bits are implemented in their version of the IP. Signed-off-by: Russell King --- drivers/gpu/drm/bridge/dw_hdmi.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/bridge/dw_hdmi.c b/drivers/gpu/drm/bridge/dw_hdmi.c index b75922d4901e..cca1c3d165e2 100644 --- a/drivers/gpu/drm/bridge/dw_hdmi.c +++ b/drivers/gpu/drm/bridge/dw_hdmi.c @@ -182,20 +182,20 @@ static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, unsigned int n) { - hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); - hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); - hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); + /* Must be set/cleared first */ + hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); /* nshift factor = 0 */ hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); - /* Must be set/cleared first */ - hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); - - hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); - hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); + hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); + hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); + + hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); + hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); + hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); } static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,