| Message ID | 20240120012948.8836-1-semen.protsenko@linaro.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | arm64: exynos: Enable SPI for Exynos850 | expand |
On Fri, 19 Jan 2024 19:29:41 -0600, Sam Protsenko wrote: > This series enables SPI for Exynos850 SoC. The summary: > > 1. Enable PDMA, it's needed for SPI (dts, clk) > 2. Propagate SPI src clock rate change up to DIV clocks, to make it > possible to change SPI frequency (clk driver) > 3. Add Exynos850 support in SPI driver > 4. Add SPI nodes to Exynos850 SoC dtsi > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next Thanks! [2/7] dt-bindings: spi: samsung: Add Exynos850 SPI commit: 737cf74b38007fd5d5d2f15d4d4bc16e5f1cbfed [5/7] spi: s3c64xx: Add Exynos850 support commit: 0229278bf33ea69cc1bba12c287f173e9b18c1f8 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
This series enables SPI for Exynos850 SoC. The summary: 1. Enable PDMA, it's needed for SPI (dts, clk) 2. Propagate SPI src clock rate change up to DIV clocks, to make it possible to change SPI frequency (clk driver) 3. Add Exynos850 support in SPI driver 4. Add SPI nodes to Exynos850 SoC dtsi All SPI instances were tested using `spidev_test' tool in all 3 possible modes: - Polling mode: xfer_size <= 32 - IRQ mode: 64 >= xfer_size >= 32 - DMA mode: xfer_size > 64 with 200 kHz ... 49.9 MHz SPI frequencies. The next 3 approaches were used: 1. Software loopback ('-l' option for `spidev_test' tool) 2. Hardware loopback (by connecting MISO line to MOSI) 3. By communicating with ATMega found on Sensors Mezzanine board [1], programmed to act as an SPI slave device and all the transactions were additionally checked on my Logic Analyzer to make sure the SCK frequencies were actually correct. [1] https://www.96boards.org/product/sensors-mezzanine/ Sam Protsenko (7): dt-bindings: clock: exynos850: Add PDMA clocks dt-bindings: spi: samsung: Add Exynos850 SPI clk: samsung: exynos850: Add PDMA clocks clk: samsung: exynos850: Propagate SPI IPCLK rate change spi: s3c64xx: Add Exynos850 support arm64: dts: exynos: Add PDMA node for Exynos850 arm64: dts: exynos: Add SPI nodes for Exynos850 .../devicetree/bindings/spi/samsung,spi.yaml | 1 + arch/arm64/boot/dts/exynos/exynos850.dtsi | 64 +++++++++++++++++++ drivers/clk/samsung/clk-exynos850.c | 42 +++++++----- drivers/spi/spi-s3c64xx.c | 14 ++++ include/dt-bindings/clock/exynos850.h | 2 + 5 files changed, 106 insertions(+), 17 deletions(-)