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[35.204.239.8]) by smtp.gmail.com with ESMTPSA id mm10-20020a170906cc4a00b00a58a44a4419sm1329562ejb.57.2024.04.25.09.03.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 09:03:49 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Subject: [PATCH 0/2] clock support for Samsung Exynos pin controller (Google Tensor gs101) Date: Thu, 25 Apr 2024 17:03:30 +0100 Message-Id: <20240425-samsung-pinctrl-busclock-v1-0-898a200abe68@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIANJ+KmYC/x3MTQqEMAxA4atI1gba+jfMVcSFxqhhnCqNiiDe3 eLyW7x3gXIQVvgmFwQ+RGXxETZNgKbWj4zSR4MzLje5K1Dbv+5+xFU8bWHGbleaF/qhLSy5rK/ KT2kg5mvgQc53XTf3/QAY9rBvagAAAA== To: Krzysztof Kozlowski , Sylwester Nawrocki , Alim Akhtar , Linus Walleij , Rob Herring , Conor Dooley , Tomasz Figa , Peter Griffin Cc: Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.12.4 This series enables clock support on the Samsung Exynos pin controller driver. This is required on Socs like Google Tensor gs101, which implement fine-grained clock control / gating, and as such a running bus clock is required for register access to work. Signed-off-by: André Draszik --- André Draszik (2): dt-bindings: pinctrl: samsung: google,gs101-pinctrl needs a clock pinctrl: samsung: support a bus clock .../bindings/pinctrl/samsung,pinctrl.yaml | 17 ++++ drivers/pinctrl/samsung/pinctrl-exynos.c | 111 +++++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 74 ++++++++++++++ drivers/pinctrl/samsung/pinctrl-samsung.h | 2 + 4 files changed, 204 insertions(+) --- base-commit: a59668a9397e7245b26e9be85d23f242ff757ae8 change-id: 20240425-samsung-pinctrl-busclock-151c23d76860 Best regards,