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[91.139.201.119]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ee0a48903sm2276459f8f.37.2024.10.20.11.21.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 11:21:52 -0700 (PDT) From: Ivaylo Ivanov To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Alim Akhtar , Rob Herring , Conor Dooley , Daniel Lezcano , Thomas Gleixner Cc: linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 0/6] arm64: dts: exynos8895: Add cmu, mct, serial_0/1 and spi_0/1 Date: Sun, 20 Oct 2024 21:21:15 +0300 Message-ID: <20241020182121.377969-1-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hey folks, This patchset adds device tree nodes for multiple clock management unit blocks, MCT, SPI and UART for Exynos8895. Exynos8895 uses USIv1 for most of its serial buses, except a few that have been implemented in this series. Support for USIv1 and HSI2C will be added in the future. This patchset is dependent on [1] and [2], which add driver support for CMU and UART. [1] https://lore.kernel.org/all/20241020174825.375096-1-ivo.ivanov.ivanov1@gmail.com/ [2] https://lore.kernel.org/all/20241020180201.376151-1-ivo.ivanov.ivanov1@gmail.com/ Ivaylo Ivanov (6): dt-bindings: timer: exynos4210-mct: Add samsung,exynos8895-mct compatible spi: dt-bindings: samsung: Add a compatible for samsung,exynos8895-spi arm64: dts: exynos: Add clock management unit nodes arm64: dts: exynos8895: Add Multi Core Timer (MCT) node arm64: dts: exynos8895: Add serial_0/1 nodes arm64: dts: exynos8895: Add spi_0/1 nodes .../devicetree/bindings/spi/samsung,spi.yaml | 4 + .../timer/samsung,exynos4210-mct.yaml | 2 + arch/arm64/boot/dts/exynos/exynos8895.dtsi | 163 ++++++++++++++++++ 3 files changed, 169 insertions(+)