From patchwork Fri Feb 1 06:20:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhilash Kesavan X-Patchwork-Id: 2076701 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 77B6FE00C6 for ; Fri, 1 Feb 2013 06:12:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755035Ab3BAGMF (ORCPT ); Fri, 1 Feb 2013 01:12:05 -0500 Received: from mailout3.samsung.com ([203.254.224.33]:31942 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754438Ab3BAGMD (ORCPT ); Fri, 1 Feb 2013 01:12:03 -0500 Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MHJ00LAN2JJ77M0@mailout3.samsung.com> for linux-samsung-soc@vger.kernel.org; Fri, 01 Feb 2013 15:12:01 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.122]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 85.FF.03880.1BC5B015; Fri, 01 Feb 2013 15:12:01 +0900 (KST) X-AuditID: cbfee61b-b7fb06d000000f28-99-510b5cb12efe Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id E4.FF.03880.1BC5B015; Fri, 01 Feb 2013 15:12:01 +0900 (KST) Received: from abhilash-ubuntu.sisodomain.com ([107.108.73.92]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MHJ003512JP2WB0@mmp1.samsung.com> for linux-samsung-soc@vger.kernel.org; Fri, 01 Feb 2013 15:12:01 +0900 (KST) From: Abhilash Kesavan To: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, kgene.kim@samsung.com Cc: kyungmin.park@samsung.com, Abhilash Kesavan Subject: [PATCH] ARM: EXYNOS5: Fix PMU register configuration for local power blocks Date: Fri, 01 Feb 2013 11:50:26 +0530 Message-id: <1359699626-28525-1-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 1.7.9.5 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrBLMWRmVeSWpSXmKPExsWyRsSkSndjDHegwb8/MhYzzu9jcmD0+LxJ LoAxissmJTUnsyy1SN8ugStj+eROpoK5ahXN72cxNjAuU+hi5OSQEDCR+LX1ExOELSZx4d56 NhBbSGApo8TSO/wwNS/mPWXsYuQCii9ilLj+azMLhLOFSeLS6e/MIFVsAnoSC/59BbNFBFIk fjztA5vKLOAuMXvfKyCbg0NYIEziy5JKkDCLgKrE9IOrGUFsXgFXib6PIGM4gJYpSMyZZAMy XkJgB5vE3abj7BD1AhLfJh9igaiRldh0gBniNkmJgytusExgFFzAyLCKUTS1ILmgOCk910iv ODG3uDQvXS85P3cTIzCcTv97Jr2DcVWDxSFGAQ5GJR7eEz+5AoVYE8uKK3MPMUpwMCuJ8C5x 5A4U4k1JrKxKLcqPLyrNSS0+xJgMtHwis5Rocj4w1PNK4g2NTcxNjU0tjYzMTE1JE1YS52U8 9SRASCA9sSQ1OzW1ILUIZgsTB6dUA+PEae4/RE3Obfi689OCyp1Xkl4L5nZ9CTHjazWe0dmX 12tzgGld5L0g/ylCqivVTr6LyUxrn7Pi7yrvs5LR1z/fFDOsXnEs1tjIuTVL+fQ9v8vKh3of z564/5E/38R9XBtVF11nsdpztHpXroFrJb9jvmtUgmX6uUCzm8nZP3cp1bmf/fBG4qsSS3FG oqEWc1FxIgChe3JuawIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupgkeLIzCtJLcpLzFFi42I5/e+xgO7GGO5Ag8YjvBYzzu9jcmD0+LxJ LoAxqoHRJiM1MSW1SCE1Lzk/JTMv3VbJOzjeOd7UzMBQ19DSwlxJIS8xN9VWycUnQNctMwdo qpJCWWJOKVAoILG4WEnfDtOE0BA3XQuYxghd35AguB4jAzSQsIYxY/nkTqaCuWoVze9nMTYw LlPoYuTkkBAwkXgx7ykjhC0mceHeerYuRi4OIYFFjBLXf21mgXC2MElcOv2dGaSKTUBPYsG/ r2C2iECKxI+nfUwgNrOAu8Tsfa+AbA4OYYEwiS9LKkHCLAKqEtMPrgZbwCvgKtH3EWQMB9Ay BYk5k2wmMHIvYGRYxSiaWpBcUJyUnmukV5yYW1yal66XnJ+7iREcrs+kdzCuarA4xCjAwajE w3viJ1egEGtiWXFl7iFGCQ5mJRHeJY7cgUK8KYmVValF+fFFpTmpxYcYk4GWT2SWEk3OB8ZS Xkm8obGJuamxqaWJhYmZJWnCSuK8jKeeBAgJpCeWpGanphakFsFsYeLglGpgjDsRobH4y48V OZo9vwWWMa/scuIqZWMVFShJZ7J/FJbBK/1y2al/597NdPJ5K/CPp/BCs/HRADWppR3WOZw/ T866OPm8bn7ci7DVolNLTnZU7Xb6PaP7yHyz29ts3nlzVc8K3XnN+bQl6+yn7zhKPix1F9uw Xb7zmc7PCp5T/+ve/noc8UnqlhJLcUaioRZzUXEiAFnM4GebAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org For the six local power blocks - MFC, DISP1, GSC, MAU, G3D and ISP the respective CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers need to be low initially for normal mode on Exynos5250. Also fix the corresponding AFTR and LPA configurations. Signed-off-by: Abhilash Kesavan --- arch/arm/mach-exynos/pmu.c | 66 ++++++++++++++++++++++++++++++++------------ 1 file changed, 48 insertions(+), 18 deletions(-) diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index daebc1a..61cedd7 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c @@ -295,24 +295,24 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = { { EXYNOS5_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, { EXYNOS5_DISP1_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, { EXYNOS5_MAU_SYS_PWR_REG, { 0x7, 0x7, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, + { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, { PMU_TABLE_END,}, }; @@ -336,6 +336,27 @@ static void __iomem *exynos5_list_diable_wfi_wfe[] = { EXYNOS5_ISP_ARM_OPTION, }; +void __iomem *exynos5_list_disable_pmu_reg[] = { + EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, + EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, + EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, + EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, + EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG, + EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG, + EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, + EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, + EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, + EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, + EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG, + EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG, + EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, + EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, + EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, + EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, + EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG, + EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG, +}; + static void exynos5_init_pmu(void) { unsigned int i; @@ -392,6 +413,7 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode) static int __init exynos_pmu_init(void) { unsigned int value; + unsigned int i; exynos_pmu_config = exynos4210_pmu_config; @@ -414,6 +436,14 @@ static int __init exynos_pmu_init(void) value &= ~EXYNOS5_SYS_WDTRESET; __raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST); + /* + * Set the CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers for + * local power blocks to Low initially as per the "System-Level + * Power-Down Configuration Registers" table. + */ + for (i = 0; i < ARRAY_SIZE(exynos5_list_disable_pmu_reg); i++) + __raw_writel(0x0, exynos5_list_disable_pmu_reg[i]); + exynos_pmu_config = exynos5250_pmu_config; pr_info("EXYNOS5250 PMU Initialize\n"); } else {