@@ -464,10 +464,9 @@
#define S5P_EINT_BASE2 (S5P_EINT_BASE1 + 16)
#define S5P_GPIOINT_BASE (S5P_EINT_BASE1 + 32)
#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
-#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64)
/* Set the default NR_IRQS */
-#define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
+#define NR_IRQS (IRQ_GPIO_END + 64)
#endif /* __ASM_ARCH_IRQS_H */
@@ -1092,12 +1092,13 @@ static struct platform_device *universal_devices[] __initdata = {
static const struct samsung_timer_variant universal_timer_variant = {
.reg_base = EXYNOS4_PA_TIMER,
.irqs = {
- IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2,
- IRQ_TIMER3, IRQ_TIMER4
+ IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
+ IRQ_TIMER3_VIC, IRQ_TIMER4_VIC
},
.bits = 32,
.prescale = 2,
.divisor = 1,
+ .has_tint_cstat = true,
};
static void __init universal_map_io(void)
@@ -225,6 +225,7 @@ static const struct samsung_timer_variant s3c24xx_timer_variant = {
.bits = 16,
.prescale = 25,
.divisor = 2,
+ .has_tint_cstat = false,
};
void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
@@ -152,12 +152,13 @@ static struct device s3c64xx_dev = {
static const struct samsung_timer_variant s3c64xx_timer_variant = {
.reg_base = S3C_PA_TIMER,
.irqs = {
- IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2,
- IRQ_TIMER3, IRQ_TIMER4
+ IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
+ IRQ_TIMER3_VIC, IRQ_TIMER4_VIC
},
.bits = 32,
.prescale = 2,
.divisor = 1,
+ .has_tint_cstat = true,
};
/* read cpu identification code */
@@ -202,9 +203,6 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
/* initialise the pair of VICs */
vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
-
- /* add the timer sub-irqs */
- s3c_init_vic_timer_irq(5, IRQ_TIMER0);
}
#define eint_offset(irq) ((irq) - IRQ_EINT(0))
@@ -107,14 +107,6 @@
#define IRQ_TC IRQ_PENDN
#define IRQ_ADC S3C64XX_IRQ_VIC1(31)
-#define S3C64XX_TIMER_IRQ(x) S3C_IRQ(64 + (x))
-
-#define IRQ_TIMER0 S3C64XX_TIMER_IRQ(0)
-#define IRQ_TIMER1 S3C64XX_TIMER_IRQ(1)
-#define IRQ_TIMER2 S3C64XX_TIMER_IRQ(2)
-#define IRQ_TIMER3 S3C64XX_TIMER_IRQ(3)
-#define IRQ_TIMER4 S3C64XX_TIMER_IRQ(4)
-
/* compatibility for device defines */
#define IRQ_IIC1 IRQ_S3C6410_IIC1
@@ -160,12 +160,13 @@ static void s5p64x0_idle(void)
static const struct samsung_timer_variant s5p64x0_timer_variant = {
.reg_base = S5P_PA_TIMER,
.irqs = {
- IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2,
- IRQ_TIMER3, IRQ_TIMER4
+ IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
+ IRQ_TIMER3_VIC, IRQ_TIMER4_VIC
},
.bits = 32,
.prescale = 2,
.divisor = 1,
+ .has_tint_cstat = true,
};
/*
@@ -141,8 +141,6 @@
#define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x))
-#define IRQ_TIMER_BASE (11)
-
/* Set the default NR_IRQS */
#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
@@ -135,12 +135,13 @@ static struct map_desc s5pc100_iodesc[] __initdata = {
static const struct samsung_timer_variant s5pc100_timer_variant = {
.reg_base = S5P_PA_TIMER,
.irqs = {
- IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2,
- IRQ_TIMER3, IRQ_TIMER4
+ IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
+ IRQ_TIMER3_VIC, IRQ_TIMER4_VIC
},
.bits = 32,
.prescale = 2,
.divisor = 1,
+ .has_tint_cstat = true,
};
/*
@@ -97,8 +97,6 @@
#define IRQ_SDMFIQ S5P_IRQ_VIC2(31)
#define IRQ_VIC_END S5P_IRQ_VIC2(31)
-#define IRQ_TIMER_BASE (11)
-
#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
@@ -152,12 +152,13 @@ void s5pv210_restart(char mode, const char *cmd)
static const struct samsung_timer_variant s5pv210_timer_variant = {
.reg_base = S5P_PA_TIMER,
.irqs = {
- IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2,
- IRQ_TIMER3, IRQ_TIMER4
+ IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
+ IRQ_TIMER3_VIC, IRQ_TIMER4_VIC
},
.bits = 32,
.prescale = 2,
.divisor = 1,
+ .has_tint_cstat = true,
};
/*
@@ -118,8 +118,6 @@
#define IRQ_MDNIE3 S5P_IRQ_VIC3(8)
#define IRQ_VIC_END S5P_IRQ_VIC3(31)
-#define IRQ_TIMER_BASE (11)
-
#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
@@ -44,15 +44,6 @@
#define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x))
#define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x))
-#define S5P_TIMER_IRQ(x) (IRQ_TIMER_BASE + (x))
-
-#define IRQ_TIMER0 S5P_TIMER_IRQ(0)
-#define IRQ_TIMER1 S5P_TIMER_IRQ(1)
-#define IRQ_TIMER2 S5P_TIMER_IRQ(2)
-#define IRQ_TIMER3 S5P_TIMER_IRQ(3)
-#define IRQ_TIMER4 S5P_TIMER_IRQ(4)
-#define IRQ_TIMER_COUNT (5)
-
#define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_EINT_BASE1) \
: ((x) - 16 + S5P_EINT_BASE2))
@@ -29,6 +29,4 @@ void __init s5p_init_irq(u32 *vic, u32 num_vic)
for (irq = 0; irq < num_vic; irq++)
vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);
#endif
-
- s3c_init_vic_timer_irq(5, IRQ_TIMER0);
}
@@ -286,6 +286,11 @@ static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
{
struct clock_event_device *evt = dev_id;
+ if (timer_variant.has_tint_cstat) {
+ u32 mask = (1 << timer_source.event_id);
+ writel(mask | (mask << 5), S3C64XX_TINT_CSTAT);
+ }
+
evt->event_handler(evt);
return IRQ_HANDLED;
@@ -322,6 +327,11 @@ static void __init samsung_clockevent_init(void)
irq_number = timer_variant.irqs[timer_source.event_id];
setup_irq(irq_number, &samsung_clock_event_irq);
+
+ if (timer_variant.has_tint_cstat) {
+ u32 mask = (1 << timer_source.event_id);
+ writel(mask | (mask << 5), S3C64XX_TINT_CSTAT);
+ }
}
static void __iomem *samsung_timer_reg(void)
@@ -36,6 +36,7 @@ struct samsung_timer_source {
* @bits: bit width of time counters
* @prescale: prescaler divisor
* @divisor: main divisor
+ * @has_tint_cstat: true if variant has TINT_CSTAT register
*/
struct samsung_timer_variant {
unsigned long reg_base;
@@ -43,6 +44,7 @@ struct samsung_timer_variant {
int bits;
u16 prescale;
u16 divisor;
+ bool has_tint_cstat;
};
extern void samsung_set_timer_source(enum samsung_timer_mode event,
Since the clocksource driver is the only user of PWM timer interrupts, there is no need to create an IRQ chip for handling them. This patch the way of PWM timer interrupt handling to use real VIC/GIC interrupt signals and handle PWM mask/ack register internally in samsung-time driver. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> --- arch/arm/mach-exynos/include/mach/irqs.h | 3 +-- arch/arm/mach-exynos/mach-universal_c210.c | 5 +++-- arch/arm/mach-s3c24xx/common.c | 1 + arch/arm/mach-s3c64xx/common.c | 8 +++----- arch/arm/mach-s3c64xx/include/mach/irqs.h | 8 -------- arch/arm/mach-s5p64x0/common.c | 5 +++-- arch/arm/mach-s5p64x0/include/mach/irqs.h | 2 -- arch/arm/mach-s5pc100/common.c | 5 +++-- arch/arm/mach-s5pc100/include/mach/irqs.h | 2 -- arch/arm/mach-s5pv210/common.c | 5 +++-- arch/arm/mach-s5pv210/include/mach/irqs.h | 2 -- arch/arm/plat-samsung/include/plat/irqs.h | 9 --------- arch/arm/plat-samsung/s5p-irq.c | 2 -- drivers/clocksource/samsung-time.c | 10 ++++++++++ include/clocksource/samsung-time.h | 2 ++ 15 files changed, 29 insertions(+), 40 deletions(-)