From patchwork Tue Mar 26 04:26:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prasanna Kumar X-Patchwork-Id: 2334591 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 57397DF264 for ; Tue, 26 Mar 2013 04:20:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756327Ab3CZEUP (ORCPT ); Tue, 26 Mar 2013 00:20:15 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:55590 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755558Ab3CZEUO (ORCPT ); Tue, 26 Mar 2013 00:20:14 -0400 Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MK900DMR2PL7OF0@mailout3.samsung.com> for linux-samsung-soc@vger.kernel.org; Tue, 26 Mar 2013 13:20:12 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.124]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id 5D.E1.07735.BF121515; Tue, 26 Mar 2013 13:20:11 +0900 (KST) X-AuditID: cbfee68e-b7f946d000001e37-e6-515121fbd68b Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 66.87.13494.BF121515; Tue, 26 Mar 2013 13:20:11 +0900 (KST) Received: from user-ubuntu.sisodomain.com ([107.108.83.235]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MK900KO92PD2V80@mmp1.samsung.com>; Tue, 26 Mar 2013 13:20:10 +0900 (KST) From: Prasanna Kumar To: linux-samsung-soc@vger.kernel.org, kgene.kim@samsung.com, linux-arm-kernel@lists.infradead.org Cc: Prasanna Kumar Subject: [PATCH] clk: exynos5250: Added MUX, DIV and GATE clocks for Gscaler and MFC Date: Tue, 26 Mar 2013 09:56:26 +0530 Message-id: <1364271986-30491-1-git-send-email-prasanna.ps@samsung.com> X-Mailer: git-send-email 1.7.5.4 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrELMWRmVeSWpSXmKPExsWyRsSkRve3YmCgwbk5Yha9C66yWWx6fI3V Ysb5fUwWs3/8ZHdg8di8pN6jb8sqRo/Pm+QCmKO4bFJSczLLUov07RK4Ml48Pcta0Glc8fbC JdYGxg1aXYycHBICJhL/O/ayQdhiEhfurQeyuTiEBJYyStzoOs4MU3TjTz8riC0ksIhRYsJX QQi7m0li/it3EJtNQE9i/ozl7CC2iECKxPdPJ1lAbGYBHYn9zzeBxYUFwiTebt/F1MXIwcEi oCqx8408SJhXwF1ie/ssdohVChK/jqxiBblBQuA2m8SUn2uYQBIsAgIS3yYfYgHplRCQldh0 AOo0SYmDK26wTGAUXMDIsIpRNLUguaA4Kb3ISK84Mbe4NC9dLzk/dxMjMPxO/3vWt4Px5gHr Q4zJQOMmMkuJJucDwzevJN7Q2MzIwtTE1NjI3NKMNGElcV61FutAIYH0xJLU7NTUgtSi+KLS nNTiQ4xMHJxSDYwrGdxmyaxNV3ti5p0+N0Vhirm3kZ08a1q1Yun67Y+cstd3G2estOGdP33f KiWrOftTf81p//bcPbustzVOWPzUV7lVG3YVbr3FsmfDDofnzIvPr3HVYOB8K+3CstKios/U VWfNyk03G+K3zje59KmT9/S2jOcsuhL9+z5zyEkcVWR8cXLm9EdKLMUZiYZazEXFiQBQERFT VQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprPIsWRmVeSWpSXmKPExsVy+t9jAd3fioGBBjf7uC16F1xls9j0+Bqr xYzz+5gsZv/4ye7A4rF5Sb1H35ZVjB6fN8kFMEc1MNpkpCampBYppOYl56dk5qXbKnkHxzvH m5oZGOoaWlqYKynkJeam2iq5+AToumXmAG1TUihLzCkFCgUkFhcr6dthmhAa4qZrAdMYoesb EgTXY2SABhLWMGa8eHqWtaDTuOLthUusDYwbtLoYOTkkBEwkbvzpZ4WwxSQu3FvPBmILCSxi lJjwVRDC7maSmP/KHcRmE9CTmD9jOTuILSKQIvH900kWEJtZQEdi//NNYHFhgTCJt9t3MXUx cnCwCKhK7HwjDxLmFXCX2N4+ix1ilYLEryOrWCcwci9gZFjFKJpakFxQnJSea6RXnJhbXJqX rpecn7uJERzcz6R3MK5qsDjEKMDBqMTDyxEWECjEmlhWXJl7iFGCg1lJhPfYBaAQb0piZVVq UX58UWlOavEhxmSg5ROZpUST84GRl1cSb2hsYm5qbGppYmFiZkmasJI478FW60AhgfTEktTs 1NSC1CKYLUwcnFINjJoSDyP2XdNO3bTuqH6i6022PO87qmFq8gEhc6bEv69WNwlx6uWeP78q u1FqdzTfVv0Hbe+vLvjsO++g0rv3T/cs/HYga/7GA7PbW/+zTVoTfW/v9zLODr0/hotkWpd2 X3USzmlNfX389+cN/P/75WQOVs+avJgz1Ylxbp/Nj+DrDdVLBJ7fuKnEUpyRaKjFXFScCAD1 10IpsgIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org From: Prasanna Kumar Gscaler : 1. For "aclk_300_gscl",following clocks are added Mux clocks mout_aclk_300_gscl_mid, mout_aclk_300_gscl_mid1, mout_aclk_300_gscl Divider clock div_aclk300_gscl Sub-Mux clock ( driven from output of divider clock) mout_sub_aclk300 2. For "aclk_266_gscl", Sub-Mux clock "mout_sub_aclk266" added Divider clock has been modified to refer Sub-Mux clock MFC : For "aclk_333" Sub-Mux clock "mout_sub_aclk333" added Divider clock has been modified to refer Sub-Mux clock Signed-off-by: Prasanna Kumar --- drivers/clk/samsung/clk-exynos5250.c | 57 +++++++++++++++++++++++++-------- 1 files changed, 43 insertions(+), 14 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index e40d6af..40dff9d 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -24,7 +24,9 @@ #define DIV_CPU0 0x500 #define SRC_CORE1 0x4204 #define SRC_TOP0 0x10210 +#define SRC_TOP1 0x10214 #define SRC_TOP2 0x10218 +#define SRC_TOP3 0x1021C #define SRC_GSCL 0x10220 #define SRC_DISP1_0 0x1022c #define SRC_MAU 0x10240 @@ -112,7 +114,9 @@ static __initdata unsigned long exynos5250_clk_regs[] = { DIV_CPU0, SRC_CORE1, SRC_TOP0, + SRC_TOP1, SRC_TOP2, + SRC_TOP3, SRC_GSCL, SRC_DISP1_0, SRC_MAU, @@ -167,6 +171,13 @@ PNAME(mout_mpll_user_p) = { "fin_pll", "sclk_mpll" }; PNAME(mout_bpll_user_p) = { "fin_pll", "sclk_bpll" }; PNAME(mout_aclk166_p) = { "sclk_cpll", "sclk_mpll_user" }; PNAME(mout_aclk200_p) = { "sclk_mpll_user", "sclk_bpll_user" }; +PNAME(mout_sub_aclk266_p) = { "fin_pll", "div_aclk266" }; +PNAME(mout_aclk_300_gscl_mid_p) = { "sclk_mpll_user", "sclk_bpll_user"}; +PNAME(mout_aclk_300_gscl_mid1_p) = { "sclk_vpll", "sclk_cpll"}; +PNAME(mout_aclk_300_gscl_p) = { "mout_aclk_300_gscl_mid", + "mout_aclk_300_gscl_mid1" }; +PNAME(mout_sub_aclk300_p) = { "fin_pll", "div_aclk300_gscl" }; +PNAME(mout_sub_aclk333_p) = { "fin_pll", "div_aclk333" }; PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" }; PNAME(mout_usb3_p) = { "sclk_mpll_user", "sclk_cpll" }; PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m", @@ -220,8 +231,20 @@ struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { MUX(none, "sclk_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1), MUX(none, "sclk_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1), MUX(none, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1), - MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1), MUX(none, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1), + MUX_A(none, "mout_sub_aclk266", mout_sub_aclk266_p, + SRC_TOP3, 8, 1, "m_sub_aclk266"), + MUX(none, "mout_aclk_300_gscl", mout_aclk_300_gscl_p, + SRC_TOP0, 25, 1), + MUX(none, "mout_aclk_300_gscl_mid", mout_aclk_300_gscl_mid_p, + SRC_TOP0, 24, 1), + MUX(none, "mout_aclk_300_gscl_mid1", mout_aclk_300_gscl_mid1_p, + SRC_TOP1, 12, 1), + MUX_A(none, "mout_sub_aclk300", mout_sub_aclk300_p, + SRC_TOP3, 10, 1, "m_sub_aclk300"), + MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1), + MUX_A(none, "mout_sub_aclk333", mout_sub_aclk333_p, + SRC_TOP3, 24, 1, "m_sub_aclk333"), MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4), MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4), MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4), @@ -257,10 +280,12 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata = { DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), DIV(none, "aclk66_pre", "sclk_mpll_user", DIV_TOP1, 24, 3), DIV(none, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3), - DIV(none, "aclk266", "sclk_mpll_user", DIV_TOP0, 16, 3), DIV(none, "aclk166", "mout_aclk166", DIV_TOP0, 8, 3), - DIV(none, "aclk333", "mout_aclk333", DIV_TOP0, 20, 3), DIV(none, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3), + DIV(none, "div_aclk266", "sclk_mpll_user", DIV_TOP0, 16, 3), + DIV(none, "div_aclk300_gscl", "mout_aclk_300_gscl", + DIV_TOP1, 14, 3), + DIV(none, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3), DIV(none, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4), DIV(none, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4), DIV(none, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4), @@ -313,19 +338,23 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata = { }; struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { - GATE(gscl0, "gscl0", "none", GATE_IP_GSCL, 0, 0, 0), - GATE(gscl1, "gscl1", "none", GATE_IP_GSCL, 1, 0, 0), - GATE(gscl2, "gscl2", "aclk266", GATE_IP_GSCL, 2, 0, 0), - GATE(gscl3, "gscl3", "aclk266", GATE_IP_GSCL, 3, 0, 0), + GATE(gscl0, "gscl0", "mout_sub_aclk266", GATE_IP_GSCL, 0, 0, 0), + GATE(gscl1, "gscl1", "mout_sub_aclk266", GATE_IP_GSCL, 1, 0, 0), + GATE(gscl2, "gscl2", "mout_sub_aclk266", GATE_IP_GSCL, 2, 0, 0), + GATE(gscl3, "gscl3", "mout_sub_aclk266", GATE_IP_GSCL, 3, 0, 0), GATE(gscl_wa, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0), GATE(gscl_wb, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0), - GATE(smmu_gscl0, "smmu_gscl0", "aclk266", GATE_IP_GSCL, 7, 0, 0), - GATE(smmu_gscl1, "smmu_gscl1", "aclk266", GATE_IP_GSCL, 8, 0, 0), - GATE(smmu_gscl2, "smmu_gscl2", "aclk266", GATE_IP_GSCL, 9, 0, 0), - GATE(smmu_gscl3, "smmu_gscl3", "aclk266", GATE_IP_GSCL, 10, 0, 0), - GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), - GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0), - GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0), + GATE(smmu_gscl0, "smmu_gscl0", "mout_sub_aclk266", + GATE_IP_GSCL, 7, 0, 0), + GATE(smmu_gscl1, "smmu_gscl1", "mout_sub_aclk266", + GATE_IP_GSCL, 8, 0, 0), + GATE(smmu_gscl2, "smmu_gscl2", "mout_sub_aclk266", + GATE_IP_GSCL, 9, 0, 0), + GATE(smmu_gscl3, "smmu_gscl3", "mout_sub_aclk266", + GATE_IP_GSCL, 10, 0, 0), + GATE(mfc, "mfc", "mout_sub_aclk333", GATE_IP_MFC, 0, 0, 0), + GATE(smmu_mfcl, "smmu_mfcl", "mout_sub_aclk333", GATE_IP_MFC, 1, 0, 0), + GATE(smmu_mfcr, "smmu_mfcr", "mout_sub_aclk333", GATE_IP_MFC, 2, 0, 0), GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0), GATE(jpeg, "jpeg", "aclk166", GATE_IP_GEN, 2, 0, 0), GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),