From patchwork Wed Mar 27 11:02:46 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 2349451 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 482633FC8C for ; Wed, 27 Mar 2013 11:06:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752098Ab3C0LGU (ORCPT ); Wed, 27 Mar 2013 07:06:20 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:43902 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751950Ab3C0LGU (ORCPT ); Wed, 27 Mar 2013 07:06:20 -0400 Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MKB0097XG6G96X0@mailout4.samsung.com> for linux-samsung-soc@vger.kernel.org; Wed, 27 Mar 2013 20:06:16 +0900 (KST) X-AuditID: cbfee61a-b7fa86d0000045ae-34-5152d2a85e7f Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 1D.DA.17838.8A2D2515; Wed, 27 Mar 2013 20:06:16 +0900 (KST) Received: from mcdsrvbld02.digital.local ([106.116.37.23]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MKB00EJ7G19TVH0@mmp2.samsung.com>; Wed, 27 Mar 2013 20:06:15 +0900 (KST) From: Tomasz Figa To: linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, kyungmin.park@samsung.com, kgene.kim@samsung.com, m.szyprowski@samsung.com, t.figa@samsung.com, s.nawrocki@samsung.com, mturquette@linaro.org, thomas.abraham@linaro.org, a.hajda@samsung.com, l.majewski@samsung.com Subject: [PATCH 09/21] clk: samsung: exynos4: Export mout_core clock of Exynos4210 Date: Wed, 27 Mar 2013 12:02:46 +0100 Message-id: <1364382178-25248-10-git-send-email-t.figa@samsung.com> X-Mailer: git-send-email 1.7.10 In-reply-to: <1364382178-25248-1-git-send-email-t.figa@samsung.com> References: <1364382178-25248-1-git-send-email-t.figa@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrILMWRmVeSWpSXmKPExsVy+t9jQd0Vl4ICDbr6+SxurTvHatG74Cqb xdmmN+wWbx5uZrTY9Pgaq8WM8/uYLNYeuctu8XTCRTaLw2/aWS3Wz3jNYnFsxhJGB26PO9f2 sHlsXlLv0bdlFaPH501yASxRXDYpqTmZZalF+nYJXBl7+s8xFWznqDi5sIu9gXERexcjJ4eE gInE2n+TGSFsMYkL99azdTFycQgJTGeUmL3iLAuE08UkMevdWzaQKjYBNYnPDY/AbBEBVYnP bQvAJjELtDJJLDxv2cXIwSEsECIx91cUSJgFqKTt5BtWEJtXwFnix9VzbBDL5CWe3u8DszmB 4u+mHwE7QkjASeLGm6esExh5FzAyrGIUTS1ILihOSs811CtOzC0uzUvXS87P3cQIDrhnUjsY VzZYHGIU4GBU4uGdwRAUKMSaWFZcmXuIUYKDWUmE1+gAUIg3JbGyKrUoP76oNCe1+BCjNAeL kjjvgVbrQCGB9MSS1OzU1ILUIpgsEwenVAPj3lwZpiXWllu75ixi5bHgqZi0d661QH3m8//M R5grEpfy7y9pEr+gObO5+JVx3o274muqj7z+mTzVPc5mVcb6Q5xu+u79mzUEPdeeENT0jnW0 POsrFHK2223VjnOn56jvXVk2z3Y2O9e5rvALSTP5K94nXTp9bf0Pw5OXfaYqXFPS5tzzIGKK EktxRqKhFnNRcSIAYhhlzTQCAAA= Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This patch enables clock lookup registration for mout_core clock used in Exynos4210 cpufreq driver. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park --- drivers/clk/samsung/clk-exynos4.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 5592a78..8c4cffb 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -311,7 +311,7 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { MUX(none, "mout_fimd1", group1_p4210, SRC_LCD1, 0, 4), MUX(none, "mout_mipi1", group1_p4210, SRC_LCD1, 12, 4), MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "sclk_mpll"), - MUX(none, "mout_core", mout_core_p4210, SRC_CPU, 16, 1), + MUX_A(mout_core, "mout_core", mout_core_p4210, SRC_CPU, 16, 1, "mout_core"), MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1, "sclk_vpll"), MUX(none, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),