From patchwork Tue Apr 2 08:20:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tushar Behera X-Patchwork-Id: 2376351 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id CE2CE3FDDA for ; Tue, 2 Apr 2013 08:32:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760233Ab3DBIcX (ORCPT ); Tue, 2 Apr 2013 04:32:23 -0400 Received: from mail-pb0-f49.google.com ([209.85.160.49]:54660 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760231Ab3DBIcT (ORCPT ); Tue, 2 Apr 2013 04:32:19 -0400 Received: by mail-pb0-f49.google.com with SMTP id um15so116476pbc.8 for ; Tue, 02 Apr 2013 01:32:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state; bh=uhQz/szZ3L0Tp2D4scrleSEP9gVtOinPEWjj1UMEXFk=; b=SES22GLt0rJ4m+FPxMqMjPzivmS7RkzaBB8//ybzX69nJlMV6LYHL/rieqeoQj3SLt C0u1SnquipU4Pyg4vOY7G4/8jQ4PBdCVaI1G9X4Dw8FvFl5sr4U+FZWUWIX1+tgSiAMO K/fIBBs+19HbWYZqzlh8id8Eb5TDj3oasrZnvKpLNYZNWRPqiYb6UdKyA/TQoM81po0H mixBvh7Cr72Ocv/i+xSUH8o/trcr/pdQPnqjC8Wu1Yo2Exto8o2cZm8w2JhhnHkwEnHO 3RlFiybaOPVnPGFQdBjfaRWjjPTewzdLmXIeYs+Aw2ZJLJuxoG9CO4isoe8ms/LKn4N5 u1fg== X-Received: by 10.68.211.37 with SMTP id mz5mr23399591pbc.83.1364891539010; Tue, 02 Apr 2013 01:32:19 -0700 (PDT) Received: from linaro.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPS id ce16sm1480848pac.5.2013.04.02.01.32.16 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 02 Apr 2013 01:32:18 -0700 (PDT) From: Tushar Behera To: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: mturquette@linaro.org, kgene.kim@samsung.com, patches@linaro.org, Thomas Abraham Subject: [PATCH] clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3} Date: Tue, 2 Apr 2013 13:50:40 +0530 Message-Id: <1364890840-20052-1-git-send-email-tushar.behera@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQmzxarrCevE/zeZePRerqAKiDMUueUIP7THyeM/DWU/DO6yWMlMrU2QRjglVoco/WwgpEIC Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org In legacy setup, sclk_mmc{0,1,2,3} used PRE_RATIO bit-field (8-bit wide) instead of RATIO bit-field (4-bit wide) for dividing clock rate. With current common clock setup, we are using RATIO bit-field which is creating FIFO read errors while accessing eMMC. Changing over to use PRE_RATIO bit-field fixes this issue. dwmmc_exynos 12200000.dwmmc0: data FIFO error (status=00008020) mmcblk0: error -5 transferring data, sector 1, nr 7, cmd response 0x900, card status 0x0 end_request: I/O error, dev mmcblk0, sector 1 Signed-off-by: Tushar Behera CC: Thomas Abraham Acked-by: Mike Turquette --- Based on Kukjin's for-next branch. commit d58f6a153f40 ("Merge branch 'next/clk-exynos-2' into for-next") drivers/clk/samsung/clk-exynos5250.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 1152125..2c46fbd 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -274,10 +274,10 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata = { DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8), DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4), - DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), - DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), - DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), - DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), + DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 8, 8), + DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 24, 8), + DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 8, 8), + DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 24, 8), DIV(none, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4), DIV(none, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4), DIV(none, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),