From patchwork Thu Apr 18 11:15:15 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sachin Kamat X-Patchwork-Id: 2459831 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 19A513FCA5 for ; Thu, 18 Apr 2013 11:27:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755388Ab3DRL1q (ORCPT ); Thu, 18 Apr 2013 07:27:46 -0400 Received: from mail-pa0-f50.google.com ([209.85.220.50]:50809 "EHLO mail-pa0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755314Ab3DRL1p (ORCPT ); Thu, 18 Apr 2013 07:27:45 -0400 Received: by mail-pa0-f50.google.com with SMTP id bg2so1538774pad.37 for ; Thu, 18 Apr 2013 04:27:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state; bh=8plx9LT3cefnEevJHAwMBqXy6tc8iVeb7nbizDGFJqA=; b=dqm9y4PBzTISEbKSMIRWJuSKNlghXQ+2/xZjWlHLqxtub8qgko7tgL6HR+U38dau2Q IRjNkAdwRux3zKHTOKNNaFzexxag58am9ORMkZ7rTKOPM2OtIeDtAtWShoAeQOsAoF// G+yfh5h3I6YDEZOU7HPRHE5HOhdhNyQX7zrBZT8m1tFDyUVu9me6vyTmaK2HyQEMIwCL Lu9KeEckKN0fauM74bp7DuJub5FqvtzG2HmYcF5UCd1KCV4+N8cC0nmQHqMFijAqJKXE PhaJBkCYp7LlT78GDxzOyR5rv2h2bosMFKYArISEGEXBwgS6QwGQB5rdYXo8mZaYrOAc 90yA== X-Received: by 10.68.218.34 with SMTP id pd2mr13142275pbc.204.1366284465268; Thu, 18 Apr 2013 04:27:45 -0700 (PDT) Received: from linaro.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPS id b3sm9626922pbw.4.2013.04.18.04.27.42 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 18 Apr 2013 04:27:44 -0700 (PDT) From: Sachin Kamat To: linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, sachin.kamat@linaro.org, patches@linaro.org, Thomas Abraham , Mike Turquette Subject: [PATCH 1/5] clk: exynos4: Add additional G2D clocks Date: Thu, 18 Apr 2013 16:45:15 +0530 Message-Id: <1366283719-9615-1-git-send-email-sachin.kamat@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQmlHRlUf6oq5WpedEEpohUbW0pSk1TByMjD1ifbNUf3rlOifCG5aVbuz3zl2mn1QhzYSy6Y Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add G2D clocks for Exynos4x12 SoC and sclk_fimg2d required by G2D IP. Signed-off-by: Sachin Kamat Cc: Thomas Abraham Cc: Mike Turquette Acked-by: Mike Turquette --- .../devicetree/bindings/clock/exynos4-clock.txt | 3 ++- drivers/clk/samsung/clk-exynos4.c | 9 +++++++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt index ea5e26f..14d5c2a 100644 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt @@ -102,6 +102,7 @@ Exynos4 SoC and this is specified where applicable. sclk_spi0_isp 174 Exynos4x12 sclk_spi1_isp 175 Exynos4x12 sclk_uart_isp 176 Exynos4x12 + sclk_fimg2d 177 [Peripheral Clock Gates] @@ -129,7 +130,7 @@ Exynos4 SoC and this is specified where applicable. smmu_mfcl 274 smmu_mfcr 275 g3d 276 - g2d 277 Exynos4210 + g2d 277 rotator 278 Exynos4210 mdma 279 Exynos4210 smmu_g2d 280 Exynos4210 diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 26f2a85..09cf161 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -152,7 +152,7 @@ enum exynos4_clks { sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2, sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1, sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp, - sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp, + sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp, sclk_fimg2d, /* gate clocks */ fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0, @@ -487,6 +487,9 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4), MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4), MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4), + MUX(none, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1), + MUX(none, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1), + MUX(none, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1), }; /* list of divider clocks supported in all exynos4 soc's */ @@ -555,7 +558,7 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = { /* list of divider clocks supported in exynos4210 soc */ static struct samsung_div_clock exynos4210_div_clks[] __initdata = { DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3), - DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4), + DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4), DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4), DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4), DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), @@ -585,6 +588,7 @@ static struct samsung_div_clock exynos4x12_div_clks[] __initdata = { DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3), DIV(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3), DIV(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3), + DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), }; /* list of gate clocks supported in all exynos4 soc's */ @@ -910,6 +914,7 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { CLK_IGNORE_UNUSED, 0), GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, CLK_IGNORE_UNUSED, 0), + GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), }; #ifdef CONFIG_OF