From patchwork Mon Apr 22 03:55:46 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sachin Kamat X-Patchwork-Id: 2469891 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 72D0FDF23A for ; Mon, 22 Apr 2013 04:08:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750711Ab3DVEIQ (ORCPT ); Mon, 22 Apr 2013 00:08:16 -0400 Received: from mail-pd0-f170.google.com ([209.85.192.170]:53888 "EHLO mail-pd0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750706Ab3DVEIQ (ORCPT ); Mon, 22 Apr 2013 00:08:16 -0400 Received: by mail-pd0-f170.google.com with SMTP id 10so3275064pdi.1 for ; Sun, 21 Apr 2013 21:08:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state; bh=oHRrqLxCrGy5f7oW+hmS87c/I33iSeD01qDkRiFzncQ=; b=VimhSYaTaQhnlwKmdNNSXAnYi5SDVJuWoyB4saqZGC0vlqMM+JndpMWI4qAiPh6JTN SGzwLzQt//lFchWmKxlRU8EslXCV9JkH0i1HL6m19WgBnp2R/e3l/R8Bgt+psLG1G9lm tTfc2qvJ3nIuNDalPQmaoU+44hmX3ip8BihjNIxUXlXpoWE8YxyKjCYVbOaafcda5LeS G4io4cBQ5WJNN2Q8NYAg0nHtk+AeWfOqyGo/nsPKqgaHbn7fCO0EGc7nNAoWVIcD/x3K 1dIJ+c4ctJ9acn81hpnSi5pzhDZWacYGWtiOjkjnN5xS74Syuu2QZD1fOQG5Ov/RcBX8 whqw== X-Received: by 10.68.180.67 with SMTP id dm3mr30349218pbc.110.1366603695708; Sun, 21 Apr 2013 21:08:15 -0700 (PDT) Received: from linaro.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPS id to7sm25288543pab.0.2013.04.21.21.08.12 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 21 Apr 2013 21:08:15 -0700 (PDT) From: Sachin Kamat To: linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, sachin.kamat@linaro.org, patches@linaro.org, Thomas Abraham , Mike Turquette Subject: [PATCH v2] clk: exynos4: Add clock entries for TMU Date: Mon, 22 Apr 2013 09:25:46 +0530 Message-Id: <1366602946-8264-1-git-send-email-sachin.kamat@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQmINqIjXW4/5zH5iu62wv4w6BVYDuX/dQM83FGqMFsoiKBKszkkJ1xsSAqAIM7iQnAnqnCe Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Added clock entries for thermal management unit (TMU) for Exynos4 SoCs. Signed-off-by: Sachin Kamat Cc: Thomas Abraham Cc: Mike Turquette --- Should be applied on top of the below patches: https://patchwork.kernel.org/patch/2448711/ https://patchwork.kernel.org/patch/2459831/ Changes since v1: Changed clock name 'tmu' to 'tmu_apbif' as per the SoC user manual. --- .../devicetree/bindings/clock/exynos4-clock.txt | 1 + drivers/clk/samsung/clk-exynos4.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt index 14d5c2a..8fc1151 100644 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt @@ -236,6 +236,7 @@ Exynos4 SoC and this is specified where applicable. spi0_isp_sclk 380 Exynos4x12 spi1_isp_sclk 381 Exynos4x12 uart_isp_sclk 382 Exynos4x12 + tmu_apbif 383 [Mux Clocks] diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 09cf161..0be7d05 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -170,7 +170,7 @@ enum exynos4_clks { gicisp, smmu_isp, smmu_drc, smmu_fd, smmu_lite0, smmu_lite1, mcuctl_isp, mpwm_isp, i2c0_isp, i2c1_isp, mtcadc_isp, pwm_isp, wdt_isp, uart_isp, asyncaxim, smmu_ispcx, spi0_isp, spi1_isp, pwm_isp_sclk, spi0_isp_sclk, - spi1_isp_sclk, uart_isp_sclk, + spi1_isp_sclk, uart_isp_sclk, tmu_apbif, /* mux clocks */ mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0, @@ -815,6 +815,7 @@ static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { GATE_A(keyif, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 0, 0, "keypad"), GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"), + GATE(tmu_apbif, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0, 0), }; /* list of gate clocks supported in exynos4x12 soc */ @@ -915,6 +916,7 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, CLK_IGNORE_UNUSED, 0), GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), + GATE(tmu_apbif, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, 0), }; #ifdef CONFIG_OF