From patchwork Thu May 2 18:01:03 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Krishna Ch X-Patchwork-Id: 2513361 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 457ADDF215 for ; Thu, 2 May 2013 18:01:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932303Ab3EBSBK (ORCPT ); Thu, 2 May 2013 14:01:10 -0400 Received: from mail-da0-f45.google.com ([209.85.210.45]:38489 "EHLO mail-da0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932081Ab3EBSBJ (ORCPT ); Thu, 2 May 2013 14:01:09 -0400 Received: by mail-da0-f45.google.com with SMTP id w3so424155dad.32 for ; Thu, 02 May 2013 11:01:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=p+vA1bC/zkBRpbNp8MdPfDQdH6eRY8SRJqltuXeZdkc=; b=OnL30OXDfwix653hp6EIyAvyaWLiALmYOVRZb+3Y2TFdrk9BmDrolqVQzt2CQnePvI kKEsdWd/0NPFj0UPoYrnmRztesymImLWJ6ZbNIVxu9mkiZGV70eR4vO7wFk8z9ch+YoU 2F9VZj3IDzgwSZ5gB2wStTToTDpbjZqdzcXpfxbkH0s/HGilcKGW/74SBVCG4F5moyJc fCqKiSYZTpsLLLapVpM1ya96X2yWo5CVDV4m3tnP74q59hYK4jPeNPWB89yQXpcLk1GP kfLVuErpxXN1jlkWmlAiooBCOnes9PcYqB2dY/Reb62HCkUlpu6yOGLGQtGVogeyfusu /NQA== X-Received: by 10.66.255.99 with SMTP id ap3mr11155446pad.102.1367517668675; Thu, 02 May 2013 11:01:08 -0700 (PDT) Received: from daisy.corp.google.com. (dhcp-172-22-52-84.mtv.corp.google.com [172.22.52.84]) by mx.google.com with ESMTPSA id fx2sm9181660pac.4.2013.05.02.11.01.07 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 02 May 2013 11:01:08 -0700 (PDT) From: Naveen Krishna Chatradhi To: linux-iio@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: jic23@cam.ac.uk, naveen@chromium.org, Naveen Krishna Chatradhi , Doug Anderson , Lars-Peter Clausen Subject: [PATCH v2] iio: adc: exynos_adc: Handle timeout issues Date: Thu, 2 May 2013 11:01:03 -0700 Message-Id: <1367517663-12225-1-git-send-email-naveenkrishna.ch@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1365048389-6364-1-git-send-email-naveenkrishna.ch@gmail.com> References: <1365048389-6364-1-git-send-email-naveenkrishna.ch@gmail.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org From: Naveen Krishna Chatradhi This patch does the following 1. use wait_for_completion_timeout instead of wait_for_completion_interruptible_timeout 2. Reset software if a timeout happens. 3. Also reduce the timeout to 100milli secs Note: submitted for review at https://patchwork.kernel.org/patch/2279591/ Signed-off-by: Naveen Krishna Chatradhi Cc: Doug Anderson Cc: Lars-Peter Clausen --- Changes since v1: As per discussion at http://marc.info/?l=linux-kernel&m=136517637228869&w=3 This patch does the following 1. use wait_for_completion_timeout instead of wait_for_completion_interruptible_timeout 2. Reset software if a timeout happens. 3. Also reduce the timeout to 100milli secs drivers/iio/adc/exynos_adc.c | 73 ++++++++++++++++++++++++------------------ 1 file changed, 42 insertions(+), 31 deletions(-) diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c index 9f3a8ef..a400bb8 100644 --- a/drivers/iio/adc/exynos_adc.c +++ b/drivers/iio/adc/exynos_adc.c @@ -81,7 +81,7 @@ enum adc_version { #define ADC_CON_EN_START (1u << 0) #define ADC_DATX_MASK 0xFFF -#define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(1000)) +#define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(100)) struct exynos_adc { void __iomem *regs; @@ -111,6 +111,35 @@ static inline unsigned int exynos_adc_get_version(struct platform_device *pdev) return (unsigned int)match->data; } +static void exynos_adc_hw_init(struct exynos_adc *info) +{ + u32 con1, con2; + int delay; + + if (info->version == ADC_V2) { + con1 = ADC_V2_CON1_SOFT_RESET; + writel(con1, ADC_V2_CON1(info->regs)); + + /* ADC H/W requires 25PCLKs before other register access */ + delay = DIV_ROUND_UP(25 * 1000000, clk_get_rate(info->clk)); + udelay(delay); + + con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL | + ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0); + writel(con2, ADC_V2_CON2(info->regs)); + + /* Enable interrupts */ + writel(1, ADC_V2_INT_EN(info->regs)); + } else { + /* set default prescaler values and Enable prescaler */ + con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN; + + /* Enable 12-bit ADC resolution */ + con1 |= ADC_V1_CON_RES; + writel(con1, ADC_V1_CON(info->regs)); + } +} + static int exynos_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, @@ -120,6 +149,7 @@ static int exynos_read_raw(struct iio_dev *indio_dev, struct exynos_adc *info = iio_priv(indio_dev); unsigned long timeout; u32 con1, con2; + int ret; if (mask != IIO_CHAN_INFO_RAW) return -EINVAL; @@ -144,16 +174,21 @@ static int exynos_read_raw(struct iio_dev *indio_dev, ADC_V1_CON(info->regs)); } - timeout = wait_for_completion_interruptible_timeout + timeout = wait_for_completion_timeout (&info->completion, EXYNOS_ADC_TIMEOUT); - *val = info->value; - mutex_unlock(&indio_dev->mlock); + if (timeout == 0) { + dev_warn(&indio_dev->dev, "Conversion timed out reseting\n"); + exynos_adc_hw_init(info); + ret = -ETIMEDOUT; + } else { + *val = info->value; + ret = IIO_VAL_INT; + } - if (timeout == 0) - return -ETIMEDOUT; + mutex_unlock(&indio_dev->mlock); - return IIO_VAL_INT; + return ret; } static irqreturn_t exynos_adc_isr(int irq, void *dev_id) @@ -225,30 +260,6 @@ static int exynos_adc_remove_devices(struct device *dev, void *c) return 0; } -static void exynos_adc_hw_init(struct exynos_adc *info) -{ - u32 con1, con2; - - if (info->version == ADC_V2) { - con1 = ADC_V2_CON1_SOFT_RESET; - writel(con1, ADC_V2_CON1(info->regs)); - - con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL | - ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0); - writel(con2, ADC_V2_CON2(info->regs)); - - /* Enable interrupts */ - writel(1, ADC_V2_INT_EN(info->regs)); - } else { - /* set default prescaler values and Enable prescaler */ - con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN; - - /* Enable 12-bit ADC resolution */ - con1 |= ADC_V1_CON_RES; - writel(con1, ADC_V1_CON(info->regs)); - } -} - static int exynos_adc_probe(struct platform_device *pdev) { struct exynos_adc *info = NULL;