From patchwork Mon May 20 14:17:08 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Sharma X-Patchwork-Id: 2593091 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id CEB7F3FD4E for ; Mon, 20 May 2013 13:54:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756825Ab3ETNyW (ORCPT ); Mon, 20 May 2013 09:54:22 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:64360 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756270Ab3ETNyV (ORCPT ); Mon, 20 May 2013 09:54:21 -0400 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MN300F6CNYJOTY0@mailout1.samsung.com> for linux-samsung-soc@vger.kernel.org; Mon, 20 May 2013 22:54:20 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.124]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id C9.44.03969.B0B2A915; Mon, 20 May 2013 22:54:19 +0900 (KST) X-AuditID: cbfee68f-b7f436d000000f81-f9-519a2b0bc2b6 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id B2.6C.16109.B0B2A915; Mon, 20 May 2013 22:54:19 +0900 (KST) Received: from chromeserver-PowerEdge-T410.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MN300ELVNVMQI60@mmp1.samsung.com>; Mon, 20 May 2013 22:54:19 +0900 (KST) From: Rahul Sharma To: linux-samsung-soc@vger.kernel.org, devicetree-discuss@lists.ozlabs.org Cc: kgene.kim@samsung.com, inki.dae@samsung.com, s.nawrocki@samsung.com, thomas.abraham@linaro.org, joshi@samsung.com, r.sh.open@gmail.com, Rahul Sharma Subject: [RFC 2/2] clk: samsung: add exynos5250 composite clock for hdmi Date: Mon, 20 May 2013 19:47:08 +0530 Message-id: <1369059428-26820-3-git-send-email-rahul.sharma@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1369059428-26820-1-git-send-email-rahul.sharma@samsung.com> References: <1369059428-26820-1-git-send-email-rahul.sharma@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrPLMWRmVeSWpSXmKPExsWyRsSkRpdbe1agwferlhYHZj9ktZh0fwKL xfddX9gtehdcZbOYcX4fk8XCF/EWUxYdZrU4/Kad1eLYjCWMDpweO2fdZfe4c20Pm8f5GQsZ Pfq2rGL0+LxJLoA1issmJTUnsyy1SN8ugStjzsTTzAXLxSvWzHjG1MB4WbiLkYNDQsBE4s1O 1y5GTiBTTOLCvfVsXYxcHEICSxklpv5ZzQqRMJH4d3gBO4gtJLCIUeLSMjWIotlMEgeubgBL sAnoSsw++IwRxBYR8JLoXrOdHaSIWWA7o8SVZffBJgkLeEg8+P6OGcRmEVCV2NKwjQ3E5gWK X7tyBGqbokT3swlgcU4BT4n9P/5AbfaQ+P/yPjPIUAmBVewSH96cZIcYJCDxbfIhFoh3ZCU2 HWCGmCMpcXDFDZYJjMILGBlWMYqmFiQXFCelFxnrFSfmFpfmpesl5+duYgQG/ul/z/p3MN49 YH2IMRlo3ERmKdHkfGDk5JXEGxqbGVmYmpgaG5lbmpEmrCTOq9ZiHSgkkJ5YkpqdmlqQWhRf VJqTWnyIkYmDU6qBUVXx0bzATcr7F/IWTFReFC+fduoU88S26q4O6WAtkyf6s491MS95PpXT Uqnkq0Nm9rZenXB2jheP/9n8NxVevd4xts7720Xll0sPVZa4VITI3Q3fGtC5oNZ+r8mEFNWf /5a94jefJdO+nCfnV+bvNYsuahznYrl/q987YP2XOR728venLn7zS4mlOCPRUIu5qDgRAJbt l7uSAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrLIsWRmVeSWpSXmKPExsVy+t9jAV1u7VmBBgt+y1kcmP2Q1WLS/Qks Ft93fWG36F1wlc1ixvl9TBYLX8RbTFl0mNXi8Jt2VotjM5YwOnB67Jx1l93jzrU9bB7nZyxk 9OjbsorR4/MmuQDWqAZGm4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwNDXUNLC3MlhbzE3FRb JRefAF23zBygg5QUyhJzSoFCAYnFxUr6dpgmhIa46VrANEbo+oYEwfUYGaCBhDWMGXMmnmYu WC5esWbGM6YGxsvCXYycHBICJhL/Di9gh7DFJC7cW88GYgsJLGKUuLRMrYuRC8iezSRx4OoG sCI2AV2J2QefMYLYIgJeEt1rtrODFDELbGeUuLLsPitIQljAQ+LB93fMIDaLgKrEloZtYFN5 geLXrhxhhdimKNH9bAJYnFPAU2L/jz/sEJs9JP6/vM88gZF3ASPDKkbR1ILkguKk9FxDveLE 3OLSvHS95PzcTYzgyHomtYNxZYPFIUYBDkYlHt6MoJmBQqyJZcWVuYcYJTiYlUR4o38DhXhT EiurUovy44tKc1KLDzEmA101kVlKNDkfGPV5JfGGxibmpsamliYWJmaWpAkrifMeaLUOFBJI TyxJzU5NLUgtgtnCxMEp1cBYWXTx1SHJJT8NdqhfOXyodl5fvUNIVVD0Xju2U12769Nv93/e luWzJXHR7OQN+oncFfXeAqYNBUcieM/2pR1uNMs/drvrxKGmbd4hcfOYPn5tWr32zHYh107e dMFPPk3H0l4Vyp7nz4/J+vDpz3TjqzmasnsnHbbg/2dyetvvT0zsDFO+zt6oxFKckWioxVxU nAgAa7Va1vACAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org HDMI driver needs to change the parent of sclk_hdmi clock to sclk_pixel or to sclk_hdmiphy, depends on the status of hdmiphy. sclk_hdmi which is gate clock doesn't support the set_parent operation. This patch adds sclk_hdmi as a composite clock which is a combination of mux clock and gate clock. Being a composite clock, above clock supports both set_parent and enable/disable functionality. Therefore hdmi driver need not be modified different S0Cs. This will handled inside CCF. Signed-off-by: Rahul Sharma --- drivers/clk/samsung/clk-exynos5250.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 5c97e75..0c9e37a 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -231,7 +231,6 @@ struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { MUX(none, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4), MUX(none, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4), MUX(none, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4), - MUX(none, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1), MUX(none, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4), MUX(none, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4), MUX(none, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4), @@ -416,8 +415,6 @@ struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0), GATE(sclk_dp, "sclk_dp", "div_dp", SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0), - GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", - SRC_MASK_DISP1_0, 20, 0, 0), GATE(sclk_audio0, "sclk_audio0", "div_audio0", SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0), GATE(sclk_mmc0, "sclk_mmc0", "div_mmc_pre0", @@ -464,6 +461,21 @@ struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { GATE(hdmi, "hdmi", "aclk200", GATE_IP_DISP1, 6, 0, 0), }; +struct samsung_composite_clock exynos5250_composite_clks[] __initdata = { + { + .id = sclk_hdmi, + .name = "sclk_hdmi", + .parent_names = mout_hdmi_p, + .num_parents = ARRAY_SIZE(mout_hdmi_p), + .mux_clk = MUX(none, NULL, mout_hdmi_p, SRC_DISP1_0, 20, + 1), + .gate_clk = GATE(none, NULL, NULL, SRC_MASK_DISP1_0, 20, + 0, 0), + .composition_flags = SAMSUNG_CLK_TYPE_GATE | + SAMSUNG_CLK_TYPE_MUX, + }, +}; + static __initdata struct of_device_id ext_clk_match[] = { { .compatible = "samsung,clock-xxti", .data = (void *)0, }, { }, @@ -515,6 +527,8 @@ void __init exynos5250_clk_init(struct device_node *np) ARRAY_SIZE(exynos5250_div_clks)); samsung_clk_register_gate(exynos5250_gate_clks, ARRAY_SIZE(exynos5250_gate_clks)); + samsung_clk_register_composite(exynos5250_composite_clks, + ARRAY_SIZE(exynos5250_composite_clks)); pr_info("Exynos5250: clock setup completed, armclk=%ld\n", _get_rate("armclk"));