From patchwork Mon Jun 3 05:19:02 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Padmavathi Venna X-Patchwork-Id: 2650741 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 9B05CDF24C for ; Mon, 3 Jun 2013 05:16:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751146Ab3FCFQi (ORCPT ); Mon, 3 Jun 2013 01:16:38 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:29340 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751069Ab3FCFQh (ORCPT ); Mon, 3 Jun 2013 01:16:37 -0400 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MNS009KEXBK9BJ0@mailout4.samsung.com> for linux-samsung-soc@vger.kernel.org; Mon, 03 Jun 2013 14:16:36 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.122]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id CC.3E.11618.4B62CA15; Mon, 03 Jun 2013 14:16:36 +0900 (KST) X-AuditID: cbfee691-b7fef6d000002d62-46-51ac26b4bdd5 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id C6.92.21068.4B62CA15; Mon, 03 Jun 2013 14:16:36 +0900 (KST) Received: from padma-linuxpc.sisodomain.com ([107.108.83.35]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MNS00MW1XAFF611@mmp2.samsung.com>; Mon, 03 Jun 2013 14:16:35 +0900 (KST) From: Padmavathi Venna To: linux-samsung-soc@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, alsa-devel@alsa-project.org, padma.v@samsung.com, padma.kvr@gmail.com Cc: sbkim73@samsung.com, broonie@kernel.org, kgene.kim@samsung.com, mturquette@linaro.org Subject: [PATCH V4 2/4] clk: samsung: register audio subsystem clocks using common clock framework Date: Mon, 03 Jun 2013 10:49:02 +0530 Message-id: <1370236744-16802-3-git-send-email-padma.v@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1370236744-16802-1-git-send-email-padma.v@samsung.com> References: <1370236744-16802-1-git-send-email-padma.v@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprMIsWRmVeSWpSXmKPExsWyRsSkSneL2ppAg7ZZkhZXLh5ispj68Amb xYHZD1ktehdcZbPY9Pgaq8WM8/uYLJ5OuMhm0b5sDqvF75vf2SwurvjC5MDlseFzE5vHzll3 2T02repk87hzbQ+bx+Yl9R7nZyxk9OjbsorR4/MmuQCOKC6blNSczLLUIn27BK6M329XMRX8 da243P+XqYHxjWUXIyeHhICJxNebR1khbDGJC/fWs3UxcnEICSxllHg5dQEbTNGZZ5uYIBLT GSX+Lp3LDOH0MEn8+zyNvYuRg4NNQEei5awLSIOIwG5Gid6LFiA2s0C0xL0nn5lAbGGBFIk/ x2ayg9gsAqoSn29+AFvAK+AscerKPahlChLHpn4Fu4hTwEVi2d2rYLYQUM2u/dtZQfZKCJxi lzj7Yz4bxCABiW+TD7GA3CAhICux6QAzxBxJiYMrbrBMYBRewMiwilE0tSC5oDgpvchUrzgx t7g0L10vOT93EyMwQk7/ezZxB+P9A9aHGJOBxk1klhJNzgdGWF5JvKGxmZGFqYmpsZG5pRlp wkrivOot1oFCAumJJanZqakFqUXxRaU5qcWHGJk4OKUaGFcwJSYr+632zKy8Gx3RcMm+8CPH TDct4dd/5sou1XmrOpUtY0XRti3a6+s+34ovn9qib1dSLhog6r92Kbfh/wYph2TOSG3Pzk9c OVrOwWFnxXTC9px3//3snHRDcQB/2uWnrGcKlp9a0Pa2W9pC/Z2C2L2Wl2KLWGw9X9X7M+b8 U3N/EP1XiaU4I9FQi7moOBEASD50vKYCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrAIsWRmVeSWpSXmKPExsVy+t9jQd0tamsCDS7e57e4cvEQk8XUh0/Y LA7Mfshq0bvgKpvFpsfXWC1mnN/HZPF0wkU2i/Zlc1gtft/8zmZxccUXJgcujw2fm9g8ds66 y+6xaVUnm8eda3vYPDYvqfc4P2Mho0ffllWMHp83yQVwRDUw2mSkJqakFimk5iXnp2Tmpdsq eQfHO8ebmhkY6hpaWpgrKeQl5qbaKrn4BOi6ZeYAHamkUJaYUwoUCkgsLlbSt8M0ITTETdcC pjFC1zckCK7HyAANJKxhzPj9dhVTwV/Xisv9f5kaGN9YdjFyckgImEicebaJCcIWk7hwbz1b FyMXh5DAdEaJv0vnMkM4PUwS/z5PY+9i5OBgE9CRaDnrAtIgIrCbUaL3ogWIzSwQLXHvyWew QcICKRJ/js1kB7FZBFQlPt/8wAZi8wo4S5y6co8NYpmCxLGpX1lBbE4BF4lld6+C2UJANbv2 b2edwMi7gJFhFaNoakFyQXFSeq6RXnFibnFpXrpecn7uJkZw/D2T3sG4qsHiEKMAB6MSDy9D zupAIdbEsuLK3EOMEhzMSiK8ySuBQrwpiZVVqUX58UWlOanFhxiTga6ayCwlmpwPTA15JfGG xibmpsamliYWJmaWpAkrifMebLUOFBJITyxJzU5NLUgtgtnCxMEp1cA4Q1Xm423GhH+ze33d 6tUV5t3WmC9cX/T00u7NRy7JTt9jzHZkj6NzmLq5IrOG4AFr2f2Xls8PVZvrKl69eL5W5YJJ /vrHTNOmGTVv/HHsjt4TLSZj6zRWvW9ZWfYsZj1mPVoh6z613zq4YcqH4wrLxR8qzf3StWDD Kj4vVzaLXvY7Ww0dp69RYinOSDTUYi4qTgQARtfWJgMDAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Audio subsystem is introduced in s5pv210 and exynos platforms. This has seperate clock controller which can control i2s0 and pcm0 clocks. This patch registers the audio subsystem clocks with the common clock framework on Exynos family. Signed-off-by: Padmavathi Venna Reviewed-by: Sylwester Nawrocki --- .../devicetree/bindings/clock/clk-exynos-audss.txt | 64 ++++++++++ drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos-audss.c | 133 ++++++++++++++++++++ include/dt-bindings/clk/exynos-audss-clk.h | 25 ++++ 4 files changed, 223 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt create mode 100644 drivers/clk/samsung/clk-exynos-audss.c create mode 100644 include/dt-bindings/clk/exynos-audss-clk.h diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt new file mode 100644 index 0000000..c401134 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt @@ -0,0 +1,64 @@ +* Samsung Audio Subsystem Clock Controller + +The Samsung Audio Subsystem clock controller generates and supplies clocks +to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock +binding described here is applicable to all SoC's in Exynos family. + +Required Properties: + +- compatible: should be one of the following: + - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs. + - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs. + +- reg: physical base address and length of the controller's register set. + +- #clock-cells: should be 1. + +The following is the list of clocks generated by the controller. Each clock is +assigned an identifier and client nodes use this identifier to specify the +clock which they consume. Some of the clocks are available only on a particular +Exynos4 SoC and this is specified where applicable. + +Provided clocks: + +Clock ID SoC (if specific) +----------------------------------------------- + +mout_audss 0 +mout_i2s 1 +dout_srp 2 +dout_bus 3 +dout_i2s 4 +srp_clk 5 +i2s_bus 6 +sclk_i2s 7 +pcm_bus 8 +sclk_pcm 9 + +Example 1: An example of a clock controller node is listed below. + +clock_audss: audss-clock-controller@3810000 { + compatible = "samsung,exynos5250-audss-clock"; + reg = <0x03810000 0x0C>; + #clock-cells = <1>; +}; + +Example 2: I2S controller node that consumes the clock generated by the clock + controller. Refer to the standard clock bindings for information + about 'clocks' and 'clock-names' property. + +i2s0: i2s@03830000 { + compatible = "samsung,i2s-v5"; + reg = <0x03830000 0x100>; + dmas = <&pdma0 10 + &pdma0 9 + &pdma0 8>; + dma-names = "tx", "rx", "tx-sec"; + clocks = <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_SCLK_I2S>, + <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_MOUT_I2S>; + clock-names = "iis", "i2s_opclk0", "i2s_opclk1", + "mout_audss", "mout_i2s"; +}; diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index b7c232e..1876810 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o +obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c new file mode 100644 index 0000000..8a77919 --- /dev/null +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * Author: Padmavathi Venna + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Common Clock Framework support for Audio Subsystem Clock Controller. +*/ + +#include +#include +#include +#include +#include + +#include + +static DEFINE_SPINLOCK(lock); +static struct clk **clk_table; +static void __iomem *reg_base; +static struct clk_onecell_data clk_data; + +#define ASS_CLK_SRC 0x0 +#define ASS_CLK_DIV 0x4 +#define ASS_CLK_GATE 0x8 + +static unsigned long reg_save[][2] = { + {ASS_CLK_SRC, 0}, + {ASS_CLK_DIV, 0}, + {ASS_CLK_GATE, 0}, +}; + +/* list of all parent clock list */ +static const char *mout_audss_p[] = { "fin_pll", "fout_epll" }; +static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" }; + +#ifdef CONFIG_PM_SLEEP +static int exynos_audss_clk_suspend(void) +{ + int i; + + for (i = 0; i < 3; i++) + reg_save[i][1] = readl(reg_base + reg_save[i][0]); + + return 0; +} + +static void exynos_audss_clk_resume(void) +{ + int i; + + for (i = 0; i < 3; i++) + writel(reg_save[i][1], reg_base + reg_save[i][0]); +} + +static struct syscore_ops exynos_audss_clk_syscore_ops = { + .suspend = exynos_audss_clk_suspend, + .resume = exynos_audss_clk_resume, +}; +#endif /* CONFIG_PM_SLEEP */ + +/* register exynos_audss clocks */ +void __init exynos_audss_clk_init(struct device_node *np) +{ + reg_base = of_iomap(np, 0); + if (!reg_base) { + pr_err("%s: failed to map audss registers\n", __func__); + return; + } + + clk_table = kzalloc(sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS, + GFP_KERNEL); + if (!clk_table) { + pr_err("%s: could not allocate clk lookup table\n", __func__); + return; + } + + clk_data.clks = clk_table; + clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS; + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + + clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss", + mout_audss_p, ARRAY_SIZE(mout_audss_p), 0, + reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); + + clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s", + mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 0, + reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); + + clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp", + "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4, + 0, &lock); + + clk_table[EXYNOS_DOUT_BUS] = clk_register_divider(NULL, "dout_bus", + "dout_srp", 0, reg_base + ASS_CLK_DIV, 4, 4, 0, + &lock); + + clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s", + "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0, + &lock); + + clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk", + "dout_srp", CLK_SET_RATE_PARENT, + reg_base + ASS_CLK_GATE, 0, 0, &lock); + + clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus", + "dout_bus", CLK_SET_RATE_PARENT, + reg_base + ASS_CLK_GATE, 2, 0, &lock); + + clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s", + "dout_i2s", CLK_SET_RATE_PARENT, + reg_base + ASS_CLK_GATE, 3, 0, &lock); + + clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus", + "sclk_pcm", CLK_SET_RATE_PARENT, + reg_base + ASS_CLK_GATE, 4, 0, &lock); + + clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm", + "div_pcm0", CLK_SET_RATE_PARENT, + reg_base + ASS_CLK_GATE, 5, 0, &lock); + +#ifdef CONFIG_PM_SLEEP + register_syscore_ops(&exynos_audss_clk_syscore_ops); +#endif + + pr_info("Exynos: Audss: clock setup completed\n"); +} +CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock", + exynos_audss_clk_init); +CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock", + exynos_audss_clk_init); diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h new file mode 100644 index 0000000..4d2d843 --- /dev/null +++ b/include/dt-bindings/clk/exynos-audss-clk.h @@ -0,0 +1,25 @@ +/* + * This header provides constants for Samsung audio subsystem + * clock controller. + * + * The constants defined in this header are being used in dts + * and exynos audss driver. + */ + +#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H +#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H + +#define EXYNOS_MOUT_AUDSS 0 +#define EXYNOS_MOUT_I2S 1 +#define EXYNOS_DOUT_SRP 2 +#define EXYNOS_DOUT_BUS 3 +#define EXYNOS_DOUT_I2S 4 +#define EXYNOS_SRP_CLK 5 +#define EXYNOS_I2S_BUS 6 +#define EXYNOS_SCLK_I2S 7 +#define EXYNOS_PCM_BUS 8 +#define EXYNOS_SCLK_PCM 9 + +#define EXYNOS_AUDSS_MAX_CLKS 10 + +#endif