From patchwork Thu Jun 6 11:01:15 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 2678921 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 59FAFDF23A for ; Thu, 6 Jun 2013 11:02:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932296Ab3FFLCf (ORCPT ); Thu, 6 Jun 2013 07:02:35 -0400 Received: from mail-pd0-f171.google.com ([209.85.192.171]:58523 "EHLO mail-pd0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932135Ab3FFLCe (ORCPT ); Thu, 6 Jun 2013 07:02:34 -0400 Received: by mail-pd0-f171.google.com with SMTP id y14so294983pdi.2 for ; Thu, 06 Jun 2013 04:02:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=XPFXX/EnoCAZJRDwkdCtNQK9EVsLkM15hLwnywGMfww=; b=ASd2YtSLKuZSvemXE1Z7RMvUAGQpB4vYXSeBM6eV2U2kPGO+KVtsJF0+oYbJEX4lXU reqp4XST4rl7ZfJ00GutvBx0PSGylXs7jvdTlshJnAGtIA6lW7ClTsxRiQJfklBqaGyx y157np/NYzZRn/lQL3734Ij+k5934VyI1YaEaFfOHNsVzqzi7Qp/Ji1WuoL36d7fPnZP QVc/SAhG1jnQK2HPgktstEQRvTCVbsS4jsWQXnQ6KMmtAjgeVapmsgzGUucPAP3arpFJ uAt+zdBHPG/kD8C9S8FeaJs+K0KK3oP8aktQGkX8e1eIT7qXeqkfIIJuNm0I0ckTe4Ew 0IQw== X-Received: by 10.66.122.130 with SMTP id ls2mr38049134pab.128.1370516554210; Thu, 06 Jun 2013 04:02:34 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id qh4sm77248213pac.8.2013.06.06.04.02.29 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 06 Jun 2013 04:02:33 -0700 (PDT) From: Chander Kashyap To: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org, kgene.kim@samsung.com, t.figa@samsung.com, s.nawrocki@samsung.com, thomas.ab@samsung.com, Chander Kashyap Subject: [PATCH 01/13] ARM: Exynos: initialize l2x0 cache controller only for cortex-a9 based SoCs Date: Thu, 6 Jun 2013 16:31:15 +0530 Message-Id: <1370516488-25860-1-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQl9C8bWFdZ8EW/a2ZtY+ZghBrvPsuh1PGpjYzOipo5kPnec/ARhtqF5eo3QFixh5Za+dXnM Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Only cortex-a9 based Exynos SoCs have l2x0 cache controller. Hence instead of checking for every SoC with soc_is_xxx, just check for cpu part number and initialize the cache controller for cortex-a9 based SoCs. Signed-off-by: Chander Kashyap --- arch/arm/mach-exynos/common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 8ce2db4..bad000e 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include @@ -520,7 +521,7 @@ static int __init exynos4_l2x0_cache_init(void) { int ret; - if (soc_is_exynos5250() || soc_is_exynos5440()) + if (read_cpuid_part_number() != ARM_CPU_PART_CORTEX_A9) return 0; ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);