From patchwork Mon Jun 10 13:24:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yadwinder Singh Brar X-Patchwork-Id: 2749571 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CDBCB9F39E for ; Wed, 19 Jun 2013 13:32:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2626D20316 for ; Wed, 19 Jun 2013 13:32:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2AA9A202F4 for ; Wed, 19 Jun 2013 13:32:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756764Ab3FSNco (ORCPT ); Wed, 19 Jun 2013 09:32:44 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:8203 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756740Ab3FSNcn (ORCPT ); Wed, 19 Jun 2013 09:32:43 -0400 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MON003S56YIKQ50@mailout2.samsung.com> for linux-samsung-soc@vger.kernel.org; Wed, 19 Jun 2013 22:32:42 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.123]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id DB.FF.29708.AF2B1C15; Wed, 19 Jun 2013 22:32:42 +0900 (KST) X-AuditID: cbfee690-b7f6f6d00000740c-68-51c1b2fa8ed2 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 77.10.21068.AF2B1C15; Wed, 19 Jun 2013 22:32:42 +0900 (KST) Received: from localhost.localdomain ([107.108.83.81]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MON00DH96XUF820@mmp2.samsung.com>; Wed, 19 Jun 2013 22:32:42 +0900 (KST) From: Yadwinder Singh Brar To: linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com, mturquette@linaro.org, thomas.abraham@linaro.org, dianders@chromium.org, t.figa@samsung.com, vikas.sajjan@linaro.org, abrestic@chromium.org, Yadwinder Singh Brar Subject: [PATCH v6 7/7] clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoC Date: Mon, 10 Jun 2013 18:54:19 +0530 Message-id: <1370870659-10929-8-git-send-email-yadi.brar@samsung.com> X-Mailer: git-send-email 1.7.0.4 In-reply-to: <1370870659-10929-1-git-send-email-yadi.brar@samsung.com> References: <1370870659-10929-1-git-send-email-yadi.brar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmplkeLIzCtJLcpLzFFi42JZI2JSrftr08FAg7ezJC1Wvv/LaHF22UE2 i94FV9ksNj2+xmox4/w+JounEy6yWayf8ZrF4tiMJYwWTx5tY7aYM/0dkwOXx+yGiywed67t YfPYvKTeo2/LKkaPz5vkAlijuGxSUnMyy1KL9O0SuDJ2tKxmLrgtVfG8YT57A+MMsS5GTg4J AROJDd/PMEPYYhIX7q1n62Lk4hASWMoo8bD3BgtM0ZoLq1ggEtMZJSb/nsYO4bQxSTxoOw3U zsHBJmAk8eqYHUiDiICqxOe2BWA1zAINTBJdm46DrRAWCJfYvXA1O4jNAlS0qvssWJxXwFVi 9ZuTrBDbFCRalx0Cq+EUcJOYsX0DG4gtBFTTcPIfI8hQCYFN7BITPnYxQQwSkPg2+RALyBES ArISmw5AvSMpcXDFDZYJjMILGBlWMYqmFiQXFCelF5noFSfmFpfmpesl5+duYgRGwel/zybs YLx3wPoQYzLQuInMUqLJ+cAoyiuJNzQ2M7IwNTE1NjK3NCNNWEmcV73FOlBIID2xJDU7NbUg tSi+qDQntfgQIxMHp1QDY9T0HMHPeT/cFgcnzZhW1hYnwyidk3KWd6ZTSCHvC0trwSe1JSJr hL+evlx9minc6u4nobm/r4QpB39o191monfwqXkG/5m49xn6+bGmp+bx3RBYv/mOy6YpO6SS rwvev2O7Wegj2+nQ64da3v+XPZumPeM2t6BA6Mwy5UU533XyrpWXLrzprMRSnJFoqMVcVJwI AHZr2ICYAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrEIsWRmVeSWpSXmKPExsVy+t9jQd1fmw4GGjzvELBY+f4vo8XZZQfZ LHoXXGWz2PT4GqvFjPP7mCyeTrjIZrF+xmsWi2MzljBaPHm0jdlizvR3TA5cHrMbLrJ43Lm2 h81j85J6j74tqxg9Pm+SC2CNamC0yUhNTEktUkjNS85PycxLt1XyDo53jjc1MzDUNbS0MFdS yEvMTbVVcvEJ0HXLzAG6SkmhLDGnFCgUkFhcrKRvh2lCaIibrgVMY4Sub0gQXI+RARpIWMOY saNlNXPBbamK5w3z2RsYZ4h1MXJySAiYSKy5sIoFwhaTuHBvPVsXIxeHkMB0RonJv6exQzht TBIP2k4zdzFycLAJGEm8OmYH0iAioCrxuW0BWA2zQAOTRNem48wgCWGBcIndC1ezg9gsQEWr us+CxXkFXCVWvznJCrFNQaJ12SGwGk4BN4kZ2zewgdhCQDUNJ/8xTmDkXcDIsIpRNLUguaA4 KT3XSK84Mbe4NC9dLzk/dxMjOMaeSe9gXNVgcYhRgINRiYfXYe7BQCHWxLLiytxDjBIczEoi vBUzgUK8KYmVValF+fFFpTmpxYcYk4GumsgsJZqcD4z/vJJ4Q2MTc1NjU0sTCxMzS9KElcR5 D7ZaBwoJpCeWpGanphakFsFsYeLglGpglFAR/1ulF5PD9ZF7zu7pqXfL069JrNy6v/iz/rkP BsLKRgXvJ57p5dpu+/Z9ZK/pwnfSoe/TPlV0tPCXXy8XWPq8j4fNQl3xvoyNwJvzlyZc85sm /5f/8GUf9edhez5/u7+s7WH1p/lmW+bFpOeluro8ublkmUqSVwPndnGn/7/m8PzgZThZq8RS nJFoqMVcVJwIAALr87/1AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, DATE_IN_PAST_96_XX, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adds the EPLL and VPLL freq table for exynos5250 SoC. Signed-off-by: Vikas Sajjan Signed-off-by: Yadwinder Singh Brar --- drivers/clk/samsung/clk-exynos5250.c | 42 ++++++++++++++++++++++++++++++++- drivers/clk/samsung/clk.h | 2 + 2 files changed, 42 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 6881810..13e293e 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -493,6 +493,29 @@ static __initdata struct of_device_id ext_clk_match[] = { { }, }; +static __initdata struct samsung_pll_rate_table vpll_24mhz_tbl[] = { + /* sorted in descending order */ + /* PLL_36XX_RATE(rate, m, p, s, k) */ + PLL_36XX_RATE(266000000, 266, 3, 3, 0), + /* Not in UM, but need for eDP on snow */ + PLL_36XX_RATE(70500000, 94, 2, 4, 0), + { }, +}; + +static __initdata struct samsung_pll_rate_table epll_24mhz_tbl[] = { + /* sorted in descending order */ + /* PLL_36XX_RATE(rate, m, p, s, k) */ + PLL_36XX_RATE(192000000, 64, 2, 2, 0), + PLL_36XX_RATE(180633600, 90, 3, 2, 20762), + PLL_36XX_RATE(180000000, 90, 3, 2, 0), + PLL_36XX_RATE(73728000, 98, 2, 4, 19923), + PLL_36XX_RATE(67737600, 90, 2, 4, 20762), + PLL_36XX_RATE(49152000, 98, 3, 4, 19923), + PLL_36XX_RATE(45158400, 90, 3, 4, 20762), + PLL_36XX_RATE(32768000, 131, 3, 5, 4719) + { }, +}; + struct __initdata samsung_pll_clock exynos5250_plls[nr_plls] = { [apll] = PLL_A(pll_35xx, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, APLL_CON0, "fout_apll", NULL), @@ -506,14 +529,16 @@ struct __initdata samsung_pll_clock exynos5250_plls[nr_plls] = { CPLL_CON0, NULL), [epll] = PLL(pll_36xx, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK, EPLL_CON0, NULL), - [vpll] = PLL(pll_36xx, fout_vpll, "fout_vpll", "fin_pll", VPLL_LOCK, - VPLL_CON0, NULL), + [vpll] = PLL(pll_36xx, fout_vpll, "fout_vpll", "mout_vpllsrc", + VPLL_LOCK, VPLL_CON0, NULL), }; /* register exynox5250 clocks */ void __init exynos5250_clk_init(struct device_node *np) { void __iomem *reg_base; + struct clk *vpllsrc; + unsigned long fin_pll_rate, mout_vpllsrc_rate = 0; if (np) { reg_base = of_iomap(np, 0); @@ -531,6 +556,19 @@ void __init exynos5250_clk_init(struct device_node *np) ext_clk_match); samsung_clk_register_mux(exynos5250_pll_pmux_clks, ARRAY_SIZE(exynos5250_pll_pmux_clks)); + + fin_pll_rate = _get_rate("fin_pll"); + + if (fin_pll_rate == (24 * MHZ)) + exynos5250_plls[epll].rate_table = epll_24mhz_tbl; + + vpllsrc = __clk_lookup("mout_vpllsrc"); + if (vpllsrc) + mout_vpllsrc_rate = clk_get_rate(vpllsrc); + + if (mout_vpllsrc_rate == (24 * MHZ)) + exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl; + samsung_clk_register_pll(exynos5250_plls, ARRAY_SIZE(exynos5250_plls), reg_base); samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks, diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index 3e6501c..378bf98 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -40,6 +40,8 @@ struct samsung_clock_alias { .alias = a, \ } +#define MHZ (1000*1000) + /** * struct samsung_fixed_rate_clock: information about fixed-rate clock * @id: platform specific id of the clock.