From patchwork Tue Jun 11 09:31:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yadwinder Singh Brar X-Patchwork-Id: 2754211 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id EC5E99F39E for ; Thu, 20 Jun 2013 09:40:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1E2DB2044C for ; Thu, 20 Jun 2013 09:40:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CA36820450 for ; Thu, 20 Jun 2013 09:39:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757349Ab3FTJjv (ORCPT ); Thu, 20 Jun 2013 05:39:51 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:53320 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755057Ab3FTJjv (ORCPT ); Thu, 20 Jun 2013 05:39:51 -0400 Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MOO00CMXQU59JY0@mailout3.samsung.com> for linux-samsung-soc@vger.kernel.org; Thu, 20 Jun 2013 18:39:50 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.125]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id CD.90.17404.5EDC2C15; Thu, 20 Jun 2013 18:39:49 +0900 (KST) X-AuditID: cbfee68d-b7f096d0000043fc-81-51c2cde5ad2f Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 6C.72.21068.5EDC2C15; Thu, 20 Jun 2013 18:39:49 +0900 (KST) Received: from localhost.localdomain ([107.108.83.81]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MOO006IBQTFAG00@mmp1.samsung.com>; Thu, 20 Jun 2013 18:39:49 +0900 (KST) From: Yadwinder Singh Brar To: linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com, mturquette@linaro.org, thomas.abraham@linaro.org, dianders@chromium.org, t.figa@samsung.com, vikas.sajjan@linaro.org, abrestic@chromium.org Subject: [PATCH v7 09/11] clk: samsung: Add set_rate() clk_ops for PLL36xx Date: Tue, 11 Jun 2013 15:01:14 +0530 Message-id: <1370943076-13461-10-git-send-email-yadi.brar@samsung.com> X-Mailer: git-send-email 1.7.0.4 In-reply-to: <1370943076-13461-1-git-send-email-yadi.brar@samsung.com> References: <1370943076-13461-1-git-send-email-yadi.brar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpgkeLIzCtJLcpLzFFi42JZI2JSq/v07KFAg98fzSxWvv/LaHF22UE2 i94FV9ksNj2+xmox4/w+JounEy6yWayf8ZrF4tiMJYwWTx5tY3bg9JjdcJHF4861PWwem5fU e/RtWcXo8XmTXABrFJdNSmpOZllqkb5dAldG/+PTbAUvFCo+3N3L2MC4VLqLkZNDQsBE4tr1 BUwQtpjEhXvr2boYuTiEBJYySpzcPpkFpujejqOsEIlFjBJXl22BctqYJFadvgHUzsHBJmAk 8eqYHUiDiICqxOe2BewgNcwCFxglmnYuBJskLOAl8bprK5jNAlS0t/U0G4jNK+Am0d27jA1i m4JE67JD7CA2J1D8Y89dMFtIwFXi3oZOsPMkBNaxS5w9eYkVYpCAxLfJh1hAjpAQkJXYdIAZ Yo6kxMEVN1gmMAovYGRYxSiaWpBcUJyUXmSoV5yYW1yal66XnJ+7iREY+qf/PevdwXj7gPUh xmSgcROZpUST84Gxk1cSb2hsZmRhamJqbGRuaUaasJI4r1qLdaCQQHpiSWp2ampBalF8UWlO avEhRiYOTqkGxv2s/lV+und0ODV2qrVrv69uWHTUPaqE4zuTwo+T/7iv3dp0oezChflatQ+V i3RUssJf+HS8XSel1r7fQM502XnjUHVZ9c8c4l9vb97rO2VSWjDD4bV51Rv3HzJ4k39AtiD5 7rG+hNl+YrxngqxLGbewbBPe9cCCv1VaPPus9nP/aFOrl3vtlFiKMxINtZiLihMBzuQAH5MC AAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrLIsWRmVeSWpSXmKPExsVy+t9jAd2nZw8FGjTf07FY+f4vo8XZZQfZ LHoXXGWz2PT4GqvFjPP7mCyeTrjIZrF+xmsWi2MzljBaPHm0jdmB02N2w0UWjzvX9rB5bF5S 79G3ZRWjx+dNcgGsUQ2MNhmpiSmpRQqpecn5KZl56bZK3sHxzvGmZgaGuoaWFuZKCnmJuam2 Si4+AbpumTlABykplCXmlAKFAhKLi5X07TBNCA1x07WAaYzQ9Q0JgusxMkADCWsYM/ofn2Yr eKFQ8eHuXsYGxqXSXYycHBICJhL3dhxlhbDFJC7cW8/WxcjFISSwiFHi6rItrBBOG5PEqtM3 mLoYOTjYBIwkXh2zA2kQEVCV+Ny2gB2khlngAqNE086FLCAJYQEvidddW8FsFqCiva2n2UBs XgE3ie7eZWwQ2xQkWpcdYgexOYHiH3vugtlCAq4S9zZ0sk1g5F3AyLCKUTS1ILmgOCk910iv ODG3uDQvXS85P3cTIziynknvYFzVYHGIUYCDUYmHV+PywUAh1sSy4srcQ4wSHMxKIrypcw4F CvGmJFZWpRblxxeV5qQWH2JMBrpqIrOUaHI+MOrzSuINjU3MTY1NLU0sTMwsSRNWEuc92God KCSQnliSmp2aWpBaBLOFiYNTqoHRP0pZIXg9883vPZ/uPTQ79OiHFOfu5S6zVdbZPDr777un 9s7s/S8Eo5j2cK3kNdyofS9djj8lZfuu2uoC/TPpiRtSL6pr3J+mKM4itO3VVt6WyU2e7g9e 3qnXfabzP87l3oLPIYuPMnFelXXn2r4q6+qfk9uW982etGbJh5/HNJgSL3eaN3srKrEUZyQa ajEXFScCALLd7FLwAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, DATE_IN_PAST_96_XX, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Vikas Sajjan This patch adds set_rate and round_rate clk_ops for PLL36xx Reviewed-by: Tomasz Figa Reviewed-by: Doug Anderson Signed-off-by: Vikas Sajjan --- drivers/clk/samsung/clk-pll.c | 79 ++++++++++++++++++++++++++++++++++++++++- 1 files changed, 78 insertions(+), 1 deletions(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index b5c8b15..66cb1cb 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -160,6 +160,8 @@ static const struct clk_ops samsung_pll35xx_clk_min_ops = { /* * PLL36xx Clock Type */ +/* Maximum lock time can be 3000 * PDIV cycles */ +#define PLL36XX_LOCK_FACTOR (3000) #define PLL36XX_KDIV_MASK (0xFFFF) #define PLL36XX_MDIV_MASK (0x1FF) @@ -168,6 +170,8 @@ static const struct clk_ops samsung_pll35xx_clk_min_ops = { #define PLL36XX_MDIV_SHIFT (16) #define PLL36XX_PDIV_SHIFT (8) #define PLL36XX_SDIV_SHIFT (0) +#define PLL36XX_KDIV_SHIFT (0) +#define PLL36XX_LOCK_STAT_SHIFT (29) static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) @@ -190,8 +194,78 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, return (unsigned long)fvco; } +static inline bool samsung_pll36xx_mpk_change( + const struct samsung_pll_rate_table *rate, u32 pll_con0, u32 pll_con1) +{ + u32 old_mdiv, old_pdiv, old_kdiv; + + old_mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK; + old_pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK; + old_kdiv = (pll_con1 >> PLL36XX_KDIV_SHIFT) & PLL36XX_KDIV_MASK; + + return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv || + rate->kdiv != old_kdiv); +} + +static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long parent_rate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 tmp, pll_con0, pll_con1; + const struct samsung_pll_rate_table *rate; + + rate = samsung_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, __clk_get_name(hw->clk)); + return -EINVAL; + } + + pll_con0 = __raw_readl(pll->con_reg); + pll_con1 = __raw_readl(pll->con_reg + 4); + + if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) { + /* If only s change, change just s value only*/ + pll_con0 &= ~(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT); + pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT); + __raw_writel(pll_con0, pll->con_reg); + + return 0; + } + + /* Set PLL lock time. */ + __raw_writel(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg); + + /* Change PLL PMS values */ + pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) | + (PLL36XX_PDIV_MASK << PLL36XX_PDIV_SHIFT) | + (PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT)); + pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) | + (rate->pdiv << PLL36XX_PDIV_SHIFT) | + (rate->sdiv << PLL36XX_SDIV_SHIFT); + __raw_writel(pll_con0, pll->con_reg); + + pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT); + pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT; + __raw_writel(pll_con1, pll->con_reg + 4); + + /* wait_lock_time */ + do { + cpu_relax(); + tmp = __raw_readl(pll->con_reg); + } while (!(tmp & (1 << PLL36XX_LOCK_STAT_SHIFT))); + + return 0; +} + static const struct clk_ops samsung_pll36xx_clk_ops = { .recalc_rate = samsung_pll36xx_recalc_rate, + .set_rate = samsung_pll36xx_set_rate, + .round_rate = samsung_pll_round_rate, +}; + +static const struct clk_ops samsung_pll36xx_clk_min_ops = { + .recalc_rate = samsung_pll36xx_recalc_rate, }; /* @@ -492,7 +566,10 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk, /* clk_ops for 36xx and 2650 are similar */ case pll_36xx: case pll_2650: - init.ops = &samsung_pll36xx_clk_ops; + if (!pll->rate_table) + init.ops = &samsung_pll36xx_clk_min_ops; + else + init.ops = &samsung_pll36xx_clk_ops; break; default: pr_warn("%s: Unknown pll type for pll clk %s\n",