From patchwork Tue Jun 11 09:31:16 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yadwinder Singh Brar X-Patchwork-Id: 2754221 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 60F9AC0AB1 for ; Thu, 20 Jun 2013 09:40:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A5E8F20448 for ; Thu, 20 Jun 2013 09:40:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9531B20451 for ; Thu, 20 Jun 2013 09:40:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965019Ab3FTJj4 (ORCPT ); Thu, 20 Jun 2013 05:39:56 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:53596 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965003Ab3FTJj4 (ORCPT ); Thu, 20 Jun 2013 05:39:56 -0400 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MOO004DXQUIU1X0@mailout2.samsung.com> for linux-samsung-soc@vger.kernel.org; Thu, 20 Jun 2013 18:39:54 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.125]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id C1.FA.03969.AEDC2C15; Thu, 20 Jun 2013 18:39:54 +0900 (KST) X-AuditID: cbfee68f-b7f436d000000f81-fb-51c2cdead84f Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 19.66.28381.AEDC2C15; Thu, 20 Jun 2013 18:39:54 +0900 (KST) Received: from localhost.localdomain ([107.108.83.81]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MOO006IBQTFAG00@mmp1.samsung.com>; Thu, 20 Jun 2013 18:39:54 +0900 (KST) From: Yadwinder Singh Brar To: linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com, mturquette@linaro.org, thomas.abraham@linaro.org, dianders@chromium.org, t.figa@samsung.com, vikas.sajjan@linaro.org, abrestic@chromium.org, Yadwinder Singh Brar Subject: [PATCH v7 11/11] clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoC Date: Tue, 11 Jun 2013 15:01:16 +0530 Message-id: <1370943076-13461-12-git-send-email-yadi.brar@samsung.com> X-Mailer: git-send-email 1.7.0.4 In-reply-to: <1370943076-13461-1-git-send-email-yadi.brar@samsung.com> References: <1370943076-13461-1-git-send-email-yadi.brar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpikeLIzCtJLcpLzFFi42JZI2JSq/vq7KFAg1N9ahYr3/9ltDi77CCb Re+Cq2wWmx5fY7WYcX4fk8XTCRfZLNbPeM1icWzGEkaLJ4+2MVvMmf6OyYHLY3bDRRaPO9f2 sHlsXlLv0bdlFaPH501yAaxRXDYpqTmZZalF+nYJXBlNO90KPkhULPuV2MB4W6SLkZNDQsBE oq99AyOELSZx4d56ti5GLg4hgaWMEo9WtbHAFB1euZAJIrGIUWLjnO2sEE4bk8SahYuBHA4O NgEjiVfH7EAaRARUJT63LWAHqWEWaGCS6Np0nBkkISwQKfH6yAt2EJsFqOjO8vtgvbwCbhJN fawQyxQkWpcdAivhBAp/7LkLZgsJuErc29AJdp2EwDp2iR/9Fxgh5ghIfJt8iAVkjoSArMSm A8wQcyQlDq64wTKBUXgBI8MqRtHUguSC4qT0ImO94sTc4tK8dL3k/NxNjMDwP/3vWf8OxrsH rA8xJgONm8gsJZqcD4yfvJJ4Q2MzIwtTE1NjI3NLM9KElcR51VqsA4UE0hNLUrNTUwtSi+KL SnNSiw8xMnFwSjUw8pyKTci17w856OxeqfRo8n3+mPWeest8fN5xHWWJLu+aocS3+dCL2g9d Ry77Rvh232S7XyGwNcjoOsO+jrwb9nus5rps8Tw+pTVIikVAZ6Ha8t2nXhwWLvf7ZrTWfhZ7 rzP35CNMnckusYmc5lJBW10zAj9fjY68mK3o7Gw4PyovM6cy3VOJpTgj0VCLuag4EQBoy1I4 lQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrPIsWRmVeSWpSXmKPExsVy+t9jAd1XZw8FGsxeLGOx8v1fRouzyw6y WfQuuMpmsenxNVaLGef3MVk8nXCRzWL9jNcsFsdmLGG0ePJoG7PFnOnvmBy4PGY3XGTxuHNt D5vH5iX1Hn1bVjF6fN4kF8Aa1cBok5GamJJapJCal5yfkpmXbqvkHRzvHG9qZmCoa2hpYa6k kJeYm2qr5OIToOuWmQN0lZJCWWJOKVAoILG4WEnfDtOE0BA3XQuYxghd35AguB4jAzSQsIYx o2mnW8EHiYplvxIbGG+LdDFyckgImEgcXrmQCcIWk7hwbz1bFyMXh5DAIkaJjXO2s0I4bUwS axYuBnI4ONgEjCReHbMDaRARUJX43LaAHaSGWaCBSaJr03FmkISwQKTE6yMv2EFsFqCiO8vv g/XyCrhJNPWxQixTkGhddgishBMo/LHnLpgtJOAqcW9DJ9sERt4FjAyrGEVTC5ILipPScw31 ihNzi0vz0vWS83M3MYKj65nUDsaVDRaHGAU4GJV4eDUuHwwUYk0sK67MPcQowcGsJMKbOudQ oBBvSmJlVWpRfnxRaU5q8SHGZKCjJjJLiSbnAyM/ryTe0NjE3NTY1NLEwsTMkjRhJXHeA63W gUIC6YklqdmpqQWpRTBbmDg4pRoY58ztYC1VCZgarxR1aIK1ONvMi1r+XC/XfNivEHVO6f+m 7UlRe3oKenONF/+qkXl7rkenK+Cp4GPrULZDOalJO/ck8BcFZ71Yd7e7abfnvxifOD2uVxHt 8zJ+KD5dub5r3wy9CYtspXNmL/gef6wg8KS4du1Gba0ThxiVs1a+nrfI7ZDYrbmvlFiKMxIN tZiLihMBL/ZHSfICAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, DATE_IN_PAST_96_XX, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Vikas Sajjan Adds the EPLL and VPLL freq table for exynos5250 SoC. Signed-off-by: Vikas Sajjan Signed-off-by: Yadwinder Singh Brar --- drivers/clk/samsung/clk-exynos5250.c | 38 ++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk.h | 2 + 2 files changed, 40 insertions(+), 0 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 492d119..2aabecb 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -498,6 +498,29 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { GATE(g3d, "g3d", "aclk_400_g3d", GATE_IP_G3D, 0, 0, 0), }; +static __initdata struct samsung_pll_rate_table vpll_24mhz_tbl[] = { + /* sorted in descending order */ + /* PLL_36XX_RATE(rate, m, p, s, k) */ + PLL_36XX_RATE(266000000, 266, 3, 3, 0), + /* Not in UM, but need for eDP on snow */ + PLL_36XX_RATE(70500000, 94, 2, 4, 0), + { }, +}; + +static __initdata struct samsung_pll_rate_table epll_24mhz_tbl[] = { + /* sorted in descending order */ + /* PLL_36XX_RATE(rate, m, p, s, k) */ + PLL_36XX_RATE(192000000, 64, 2, 2, 0), + PLL_36XX_RATE(180633600, 90, 3, 2, 20762), + PLL_36XX_RATE(180000000, 90, 3, 2, 0), + PLL_36XX_RATE(73728000, 98, 2, 4, 19923), + PLL_36XX_RATE(67737600, 90, 2, 4, 20762), + PLL_36XX_RATE(49152000, 98, 3, 4, 19923), + PLL_36XX_RATE(45158400, 90, 3, 4, 20762), + PLL_36XX_RATE(32768000, 131, 3, 5, 4719), + { }, +}; + struct __initdata samsung_pll_clock exynos5250_plls[nr_plls] = { [apll] = PLL_A(pll_35xx, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, APLL_CON0, "fout_apll", NULL), @@ -524,6 +547,8 @@ static __initdata struct of_device_id ext_clk_match[] = { static void __init exynos5250_clk_init(struct device_node *np) { void __iomem *reg_base; + struct clk *vpllsrc; + unsigned long fin_pll_rate, mout_vpllsrc_rate = 0; if (np) { reg_base = of_iomap(np, 0); @@ -541,6 +566,19 @@ static void __init exynos5250_clk_init(struct device_node *np) ext_clk_match); samsung_clk_register_mux(exynos5250_pll_pmux_clks, ARRAY_SIZE(exynos5250_pll_pmux_clks)); + + fin_pll_rate = _get_rate("fin_pll"); + + if (fin_pll_rate == 24 * MHZ) + exynos5250_plls[epll].rate_table = epll_24mhz_tbl; + + vpllsrc = __clk_lookup("mout_vpllsrc"); + if (vpllsrc) + mout_vpllsrc_rate = clk_get_rate(vpllsrc); + + if (mout_vpllsrc_rate == 24 * MHZ) + exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl; + samsung_clk_register_pll(exynos5250_plls, ARRAY_SIZE(exynos5250_plls), reg_base); samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks, diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index 4a003d7..d459ef7 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -40,6 +40,8 @@ struct samsung_clock_alias { .alias = a, \ } +#define MHZ (1000 * 1000) + /** * struct samsung_fixed_rate_clock: information about fixed-rate clock * @id: platform specific id of the clock.