From patchwork Tue Jun 11 09:31:13 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yadwinder Singh Brar X-Patchwork-Id: 2754191 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0C0B4C0AB1 for ; Thu, 20 Jun 2013 09:40:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CB79820451 for ; Thu, 20 Jun 2013 09:39:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E861C20448 for ; Thu, 20 Jun 2013 09:39:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757374Ab3FTJjt (ORCPT ); Thu, 20 Jun 2013 05:39:49 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:53314 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755057Ab3FTJjs (ORCPT ); Thu, 20 Jun 2013 05:39:48 -0400 Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MOO00CMXQU59JY0@mailout3.samsung.com> for linux-samsung-soc@vger.kernel.org; Thu, 20 Jun 2013 18:39:47 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.125]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id A8.90.17404.3EDC2C15; Thu, 20 Jun 2013 18:39:47 +0900 (KST) X-AuditID: cbfee68d-b7f096d0000043fc-63-51c2cde3a9b2 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 1B.72.21068.3EDC2C15; Thu, 20 Jun 2013 18:39:47 +0900 (KST) Received: from localhost.localdomain ([107.108.83.81]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MOO006IBQTFAG00@mmp1.samsung.com>; Thu, 20 Jun 2013 18:39:47 +0900 (KST) From: Yadwinder Singh Brar To: linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com, mturquette@linaro.org, thomas.abraham@linaro.org, dianders@chromium.org, t.figa@samsung.com, vikas.sajjan@linaro.org, abrestic@chromium.org, Yadwinder Singh Brar Subject: [PATCH v7 08/11] clk: samsung: Add set_rate() clk_ops for PLL35xx Date: Tue, 11 Jun 2013 15:01:13 +0530 Message-id: <1370943076-13461-9-git-send-email-yadi.brar@samsung.com> X-Mailer: git-send-email 1.7.0.4 In-reply-to: <1370943076-13461-1-git-send-email-yadi.brar@samsung.com> References: <1370943076-13461-1-git-send-email-yadi.brar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmplkeLIzCtJLcpLzFFi42JZI2JSq/v47KFAgwNrVS1Wvv/LaHF22UE2 i94FV9ksNj2+xmox4/w+JounEy6yWayf8ZrF4tiMJYwWTx5tY7aYM/0dkwOXx+yGiywed67t YfPYvKTeo2/LKkaPz5vkAlijuGxSUnMyy1KL9O0SuDJ6V61nKbipUnHx4grWBsbvsl2MnBwS AiYSE85PZ4SwxSQu3FvP1sXIxSEksJRRoqtrGytM0bNbD9ghEosYJRoaYJw2Jom2Fd1MXYwc HGwCRhKvjtmBNIgIqEp8blsAVsMs0MAk0bXpODNIQljAS+L7twY2EJsFqOjD1O1MIDavgKvE /YWT2CC2KUi0LjvEDmJzCrhJfOy5C2YLAdXc29AJdp6EwDZ2icXzN7NCDBKQ+Db5EAvIERIC shKbDjBDzJGUOLjiBssERuEFjAyrGEVTC5ILipPSiwz1ihNzi0vz0vWS83M3MQKj4PS/Z707 GG8fsD7EmAw0biKzlGhyPjCK8kriDY3NjCxMTUyNjcwtzUgTVhLnVWuxDhQSSE8sSc1OTS1I LYovKs1JLT7EyMTBKdXAWK++TeUGv7bohYkSiatiylMN5c1apR4qf5zM8Tphzb1lXDH75/yM OzJ3uvF9fadpv+78usv02srifM6huMuxYlyysbneom7Pnp1UjP9mtfvT/o0yV98t7zqceTx2 /v1rEcncF//aPsxduqjYILsmzsLwJnupcUW9RNcX20+3Hj/a/PRnpMmrVUosxRmJhlrMRcWJ AMFVJrKYAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrEIsWRmVeSWpSXmKPExsVy+t9jAd3HZw8FGpxaImOx8v1fRouzyw6y WfQuuMpmsenxNVaLGef3MVk8nXCRzWL9jNcsFsdmLGG0ePJoG7PFnOnvmBy4PGY3XGTxuHNt D5vH5iX1Hn1bVjF6fN4kF8Aa1cBok5GamJJapJCal5yfkpmXbqvkHRzvHG9qZmCoa2hpYa6k kJeYm2qr5OIToOuWmQN0lZJCWWJOKVAoILG4WEnfDtOE0BA3XQuYxghd35AguB4jAzSQsIYx o3fVepaCmyoVFy+uYG1g/C7bxcjJISFgIvHs1gN2CFtM4sK99WxdjFwcQgKLGCUaGkASIE4b k0Tbim6mLkYODjYBI4lXx+xAGkQEVCU+ty0Aq2EWaGCS6Np0nBkkISzgJfH9WwMbiM0CVPRh 6nYmEJtXwFXi/sJJbBDbFCRalx0C28wp4CbxsecumC0EVHNvQyfbBEbeBYwMqxhFUwuSC4qT 0nON9IoTc4tL89L1kvNzNzGCY+yZ9A7GVQ0WhxgFOBiVeHg1Lh8MFGJNLCuuzD3EKMHBrCTC mzrnUKAQb0piZVVqUX58UWlOavEhxmSgqyYyS4km5wPjP68k3tDYxNzU2NTSxMLEzJI0YSVx 3oOt1oFCAumJJanZqakFqUUwW5g4OKUaGMWCNe5yN4UfcvaYY8f/VqDlnj3TiqZX78MLW1fp KsrMLtEvi7VZ/6Dd/UrOru6Sif33a1jX7f/2eIpCMTv7keuhGmdUXlyzv1jz4YjdzUdV2dO/ Le1YMS03Sns5m6/Sm5hPJp/VfGvuPc3mffTrfbDbC89NW0PmnfohH7bjmP6UZV8fGSRWJCix FGckGmoxFxUnAgCoifvM9QIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, DATE_IN_PAST_96_XX, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch add set_rate() and round_rate() for PLL35xx Reviewed-by: Doug Anderson Reviewed-by: Tomasz Figa Signed-off-by: Yadwinder Singh Brar --- drivers/clk/samsung/clk-pll.c | 105 ++++++++++++++++++++++++++++++++++++++++- 1 files changed, 104 insertions(+), 1 deletions(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index adc0659..b5c8b15 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -24,16 +24,51 @@ struct samsung_clk_pll { #define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw) +static const struct samsung_pll_rate_table *samsung_get_pll_settings( + struct samsung_clk_pll *pll, unsigned long rate) +{ + const struct samsung_pll_rate_table *rate_table = pll->rate_table; + int i; + + for (i = 0; i < pll->rate_count; i++) { + if (rate == rate_table[i].rate) + return &rate_table[i]; + } + + return NULL; +} + +static long samsung_pll_round_rate(struct clk_hw *hw, + unsigned long drate, unsigned long *prate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + const struct samsung_pll_rate_table *rate_table = pll->rate_table; + int i; + + /* Assumming rate_table is in descending order */ + for (i = 0; i < pll->rate_count; i++) { + if (drate >= rate_table[i].rate) + return rate_table[i].rate; + } + + /* return minimum supported value */ + return rate_table[i - 1].rate; +} + /* * PLL35xx Clock Type */ +/* Maximum lock time can be 270 * PDIV cycles */ +#define PLL35XX_LOCK_FACTOR (270) #define PLL35XX_MDIV_MASK (0x3FF) #define PLL35XX_PDIV_MASK (0x3F) #define PLL35XX_SDIV_MASK (0x7) +#define PLL35XX_LOCK_STAT_MASK (0x1) #define PLL35XX_MDIV_SHIFT (16) #define PLL35XX_PDIV_SHIFT (8) #define PLL35XX_SDIV_SHIFT (0) +#define PLL35XX_LOCK_STAT_SHIFT (29) static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) @@ -53,8 +88,73 @@ static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw, return (unsigned long)fvco; } +static inline bool samsung_pll35xx_mp_change( + const struct samsung_pll_rate_table *rate, u32 pll_con) +{ + u32 old_mdiv, old_pdiv; + + old_mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK; + old_pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK; + + return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv); +} + +static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + const struct samsung_pll_rate_table *rate; + u32 tmp; + + /* Get required rate settings from table */ + rate = samsung_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, __clk_get_name(hw->clk)); + return -EINVAL; + } + + tmp = __raw_readl(pll->con_reg); + + if (!(samsung_pll35xx_mp_change(rate, tmp))) { + /* If only s change, change just s value only*/ + tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT); + tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT; + __raw_writel(tmp, pll->con_reg); + + return 0; + } + + /* Set PLL lock time. */ + __raw_writel(rate->pdiv * PLL35XX_LOCK_FACTOR, + pll->lock_reg); + + /* Change PLL PMS values */ + tmp &= ~((PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT) | + (PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT) | + (PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT)); + tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) | + (rate->pdiv << PLL35XX_PDIV_SHIFT) | + (rate->sdiv << PLL35XX_SDIV_SHIFT); + __raw_writel(tmp, pll->con_reg); + + /* wait_lock_time */ + do { + cpu_relax(); + tmp = __raw_readl(pll->con_reg); + } while (!(tmp & (PLL35XX_LOCK_STAT_MASK + << PLL35XX_LOCK_STAT_SHIFT))); + return 0; +} + static const struct clk_ops samsung_pll35xx_clk_ops = { .recalc_rate = samsung_pll35xx_recalc_rate, + .round_rate = samsung_pll_round_rate, + .set_rate = samsung_pll35xx_set_rate, +}; + +static const struct clk_ops samsung_pll35xx_clk_min_ops = { + .recalc_rate = samsung_pll35xx_recalc_rate, }; /* @@ -384,7 +484,10 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk, /* clk_ops for 35xx and 2550 are similar */ case pll_35xx: case pll_2550: - init.ops = &samsung_pll35xx_clk_ops; + if (!pll->rate_table) + init.ops = &samsung_pll35xx_clk_min_ops; + else + init.ops = &samsung_pll35xx_clk_ops; break; /* clk_ops for 36xx and 2650 are similar */ case pll_36xx: