From patchwork Tue Jun 11 14:11:28 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Sharma X-Patchwork-Id: 2704351 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id C9BE1DF23A for ; Tue, 11 Jun 2013 13:51:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751764Ab3FKNvv (ORCPT ); Tue, 11 Jun 2013 09:51:51 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:52902 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751464Ab3FKNvu (ORCPT ); Tue, 11 Jun 2013 09:51:50 -0400 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MO8000O3EI6O540@mailout1.samsung.com> for linux-samsung-soc@vger.kernel.org; Tue, 11 Jun 2013 22:51:49 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.125]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id 33.B9.11618.57B27B15; Tue, 11 Jun 2013 22:51:49 +0900 (KST) X-AuditID: cbfee691-b7fef6d000002d62-2d-51b72b7582d8 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id C5.F4.21068.57B27B15; Tue, 11 Jun 2013 22:51:49 +0900 (KST) Received: from chromeserver-PowerEdge-T410.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MO80097REB7UU70@mmp2.samsung.com>; Tue, 11 Jun 2013 22:51:49 +0900 (KST) From: Rahul Sharma To: linux-samsung-soc@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, dri-devel@lists.freedesktop.org Cc: kgene.kim@samsung.com, sw0312.kim@samsung.com, inki.dae@samsung.com, joshi@samsung.com, r.sh.open@gmail.com, Rahul Sharma Subject: [PATCH 6/9] drm/exynos: fix interlace resolutions for exynos5420 Date: Tue, 11 Jun 2013 19:41:28 +0530 Message-id: <1370959891-8923-7-git-send-email-rahul.sharma@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1370959891-8923-1-git-send-email-rahul.sharma@samsung.com> References: <1370959891-8923-1-git-send-email-rahul.sharma@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrPLMWRmVeSWpSXmKPExsWyRsSkVrdUe3ugwYeJGhYHZj9ktbjy9T2b xaT7E1gsvu/6wm7Ru+Aqm8WM8/uYLBa+iLeYsugwq8WMyS/ZHDg9ds66y+5xv/s4k8f5GQsZ Pfq2rGL0+LxJLoA1issmJTUnsyy1SN8ugStj8Zp+9oJ/4hXz/1xkbWDsE+li5OSQEDCRmLZk BTuELSZx4d56NhBbSGApo8TlvZ4wNdvO/WLpYuQCik9nlLj65wkrhDObSeJnbyczSBWbgK7E 7IPPGEFsEYFciYa/7WAdzAKzGCW+zz4DtIKDQ1jAU+LNSR6QGhYBVYkvs2aAbeMVcJeYuH8N M8Q2RYnuZxPA4pwCHhI9DZeYIS5yl2j808wIMlNCYB27xKkLF5khBglIfJt8iAVkvoSArMSm A1BzJCUOrrjBMoFReAEjwypG0dSC5ILipPQiU73ixNzi0rx0veT83E2MwMA//e/ZxB2M9w9Y H2JMBho3kVlKNDkfGDl5JfGGxmZGFqYmpsZG5pZmpAkrifOqt1gHCgmkJ5akZqemFqQWxReV 5qQWH2Jk4uCUamCMXnpC+s3hmmOHnvx5+n3J5DvLLkonv9WvXep0fc+eJVM8I1MTmzlUnyyy rSlPNZ765OVJjulaPeXTzu9ryLbPjfP64MQYJZ8vq/iuIenvjNDFe1nUa5V5ZVZL9keeZf92 w6+D93Ve+s00h5o0+xKlef7RkU7rttbpL9zmJJK7Utjvpm6JwW4lluKMREMt5qLiRAAXYXba kgIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrLIsWRmVeSWpSXmKPExsVy+t9jQd1S7e2BBq9OyVkcmP2Q1eLK1/ds FpPuT2Cx+L7rC7tF74KrbBYzzu9jslj4It5iyqLDrBYzJr9kc+D02DnrLrvH/e7jTB7nZyxk 9OjbsorR4/MmuQDWqAZGm4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwNDXUNLC3MlhbzE3FRb JRefAF23zBygg5QUyhJzSoFCAYnFxUr6dpgmhIa46VrANEbo+oYEwfUYGaCBhDWMGYvX9LMX /BOvmP/nImsDY59IFyMnh4SAicS2c79YIGwxiQv31rN1MXJxCAlMZ5S4+ucJK4Qzm0niZ28n M0gVm4CuxOyDzxhBbBGBXImGv+0sIEXMArMYJb7PPsPexcjBISzgKfHmJA9IDYuAqsSXWTPY QGxeAXeJifvXMENsU5TofjYBLM4p4CHR03AJLC4EVNP4p5lxAiPvAkaGVYyiqQXJBcVJ6blG esWJucWleel6yfm5mxjBkfVMegfjqgaLQ4wCHIxKPLwJjNsChVgTy4orcw8xSnAwK4nwNspt DxTiTUmsrEotyo8vKs1JLT7EmAx01URmKdHkfGDU55XEGxqbmJsam1qaWJiYWZImrCTOe7DV OlBIID2xJDU7NbUgtQhmCxMHp1QDY1JC9aem54a8mSaHjH/mKS+cHOjrdu3LU8sL185131h2 Y2Zn2pSyugR2tmzveY7zXr+Ldjtgu8qzoUXrf4y14toLXIKMHGlWStOsnty/ad1d8vBgjlVm Ep98/s69HQJP1z1PVp/8LCBl0215jmr5rLklucVmljNcvVz/bMre2pfM+auPS3KXEktxRqKh FnNRcSIACDsNQ/ACAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Modified code for calculating hdmi IP register values from drm timing values. The modification is based on the inputs from hw team and specifically proposed for 1440x576i and 1440x480i. But same changes holds good for other interlaced resolutions also. Signed-off-by: Rahul Sharma --- drivers/gpu/drm/exynos/exynos_hdmi.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 423bdc6..1eb5ffb 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -1767,8 +1767,7 @@ static void hdmi_4212_mode_set(struct hdmi_context *hdata, (m->vsync_start - m->vdisplay) / 2); hdmi_set_reg(core->v2_blank, 2, m->vtotal / 2); hdmi_set_reg(core->v1_blank, 2, (m->vtotal - m->vdisplay) / 2); - hdmi_set_reg(core->v_blank_f0, 2, (m->vtotal + - ((m->vsync_end - m->vsync_start) * 4) + 5) / 2); + hdmi_set_reg(core->v_blank_f0, 2, m->vtotal - m->vdisplay / 2); hdmi_set_reg(core->v_blank_f1, 2, m->vtotal); hdmi_set_reg(core->v_sync_line_aft_2, 2, (m->vtotal / 2) + 7); hdmi_set_reg(core->v_sync_line_aft_1, 2, (m->vtotal / 2) + 2); @@ -1778,7 +1777,10 @@ static void hdmi_4212_mode_set(struct hdmi_context *hdata, (m->htotal / 2) + (m->hsync_start - m->hdisplay)); hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2); hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2); - hdmi_set_reg(tg->vact_st2, 2, 0x249);/* Reset value + 1*/ + hdmi_set_reg(tg->vact_st2, 2, m->vtotal - m->vdisplay / 2); + hdmi_set_reg(tg->vsync2, 2, (m->vtotal / 2) + 1); + hdmi_set_reg(tg->vsync_bot_hdmi, 2, (m->vtotal / 2) + 1); + hdmi_set_reg(tg->field_bot_hdmi, 2, (m->vtotal / 2) + 1); hdmi_set_reg(tg->vact_st3, 2, 0x0); hdmi_set_reg(tg->vact_st4, 2, 0x0); } else { @@ -1800,6 +1802,9 @@ static void hdmi_4212_mode_set(struct hdmi_context *hdata, hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */ hdmi_set_reg(tg->vact_st3, 2, 0x47b); /* Reset value */ hdmi_set_reg(tg->vact_st4, 2, 0x6ae); /* Reset value */ + hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */ + hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */ + hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */ } /* Following values & calculations are same irrespective of mode type */ @@ -1831,12 +1836,9 @@ static void hdmi_4212_mode_set(struct hdmi_context *hdata, hdmi_set_reg(tg->hact_sz, 2, m->hdisplay); hdmi_set_reg(tg->v_fsz, 2, m->vtotal); hdmi_set_reg(tg->vsync, 2, 0x1); - hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */ hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */ hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */ - hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */ hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */ - hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */ hdmi_set_reg(tg->tg_3d, 1, 0x0); }