From patchwork Fri Jun 14 19:33:04 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 2723641 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3BC20C0AB2 for ; Fri, 14 Jun 2013 19:33:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5F6D42036D for ; Fri, 14 Jun 2013 19:33:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4ABF520368 for ; Fri, 14 Jun 2013 19:33:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752134Ab3FNTdl (ORCPT ); Fri, 14 Jun 2013 15:33:41 -0400 Received: from mailout1.w1.samsung.com ([210.118.77.11]:31659 "EHLO mailout1.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753906Ab3FNTdf (ORCPT ); Fri, 14 Jun 2013 15:33:35 -0400 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout1.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MOE00FZSE9PI770@mailout1.w1.samsung.com> for linux-samsung-soc@vger.kernel.org; Fri, 14 Jun 2013 20:33:31 +0100 (BST) X-AuditID: cbfec7f4-b7fd76d0000035e1-cf-51bb700b39a7 Received: from eusync2.samsung.com ( [203.254.199.212]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id 9A.59.13793.B007BB15; Fri, 14 Jun 2013 20:33:31 +0100 (BST) Received: from amdc1227.digital.local ([106.116.147.199]) by eusync2.samsung.com (Oracle Communications Messaging Server 7u4-23.01(7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0MOE00FXFEBEW970@eusync2.samsung.com>; Fri, 14 Jun 2013 20:33:31 +0100 (BST) From: Tomasz Figa To: linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Kukjin Kim , Arnd Bergmann , Olof Johansson , Marek Szyprowski , Sylwester Nawrocki , Thomas Abraham , Tomasz Figa , Kyungmin Park Subject: [PATCH 28/28] ARM: EXYNOS: Remove mach/regs-usb-phy.h header Date: Fri, 14 Jun 2013 21:33:04 +0200 Message-id: <1371238384-1504-29-git-send-email-t.figa@samsung.com> X-Mailer: git-send-email 1.8.2.1 In-reply-to: <1371238384-1504-1-git-send-email-t.figa@samsung.com> References: <1371238384-1504-1-git-send-email-t.figa@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmplluLIzCtJLcpLzFFi42I5/e/4FV3ugt2BBsv3i1n8nXSM3aJ3wVU2 i7NNb9gtNj2+xmox4/w+Jou1R+6yW5y6/pnN4vCbdlaL9TNes1gcm7GE0YHL4/evSYwed67t YfPYvKTe48qJJlaPvi2rGD0+b5ILYIvisklJzcksSy3St0vgylj/t4GpYKpkxc6Tp1kaGH+L dDFyckgImEg8W3WOGcIWk7hwbz0biC0ksJRRYsM3Xwi7j0mi60E2iM0moCbxueERWI2IgKrE 57YF7F2MXBzMAi+ZJO42PgByODiEBVwlth3JBjFZgGqunJEAMXkFnCSmTvOC2KQgcXz7NkYQ mxMofHb9FqitjhLTG5ewTGDkXcDIsIpRNLU0uaA4KT3XUK84Mbe4NC9dLzk/dxMjJOi+7GBc fMzqEKMAB6MSD+9Etd2BQqyJZcWVuYcYJTiYlUR476oChXhTEiurUovy44tKc1KLDzEycXBK NTAaTupq5ngryH2RcQ7znahAxsVNt66vLn03Y3HvtdBlx1XC/DKVe3rZ/25/WRZbpzr12JYd mzdsl+SteO/1aRpH2LtOZbm7p0/turj8uziznWOk27+gdwsCEl5FdijcM2Q83LXC4tMZuTCJ 6JQe6WqbUNaFrBEdZy9cvOq09s9Dmyn3t4fJrz2oxFKckWioxVxUnAgA7QwLrRgCAAA= Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch removes mach/regs-usb-phy.h header, which is not used anywhere in the kernel. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park --- arch/arm/mach-exynos/include/mach/regs-usb-phy.h | 74 ------------------------ 1 file changed, 74 deletions(-) delete mode 100644 arch/arm/mach-exynos/include/mach/regs-usb-phy.h diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h deleted file mode 100644 index 0727773..0000000 --- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (C) 2011 Samsung Electronics Co.Ltd - * Author: Joonyoung Shim - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __PLAT_S5P_REGS_USB_PHY_H -#define __PLAT_S5P_REGS_USB_PHY_H - -#define EXYNOS4_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY) - -#define EXYNOS4_PHYPWR EXYNOS4_HSOTG_PHYREG(0x00) -#define PHY1_HSIC_NORMAL_MASK (0xf << 9) -#define PHY1_HSIC1_SLEEP (1 << 12) -#define PHY1_HSIC1_FORCE_SUSPEND (1 << 11) -#define PHY1_HSIC0_SLEEP (1 << 10) -#define PHY1_HSIC0_FORCE_SUSPEND (1 << 9) - -#define PHY1_STD_NORMAL_MASK (0x7 << 6) -#define PHY1_STD_SLEEP (1 << 8) -#define PHY1_STD_ANALOG_POWERDOWN (1 << 7) -#define PHY1_STD_FORCE_SUSPEND (1 << 6) - -#define PHY0_NORMAL_MASK (0x39 << 0) -#define PHY0_SLEEP (1 << 5) -#define PHY0_OTG_DISABLE (1 << 4) -#define PHY0_ANALOG_POWERDOWN (1 << 3) -#define PHY0_FORCE_SUSPEND (1 << 0) - -#define EXYNOS4_PHYCLK EXYNOS4_HSOTG_PHYREG(0x04) -#define PHY1_COMMON_ON_N (1 << 7) -#define PHY0_COMMON_ON_N (1 << 4) -#define PHY0_ID_PULLUP (1 << 2) - -#define EXYNOS4_CLKSEL_SHIFT (0) - -#define EXYNOS4210_CLKSEL_MASK (0x3 << 0) -#define EXYNOS4210_CLKSEL_48M (0x0 << 0) -#define EXYNOS4210_CLKSEL_12M (0x2 << 0) -#define EXYNOS4210_CLKSEL_24M (0x3 << 0) - -#define EXYNOS4X12_CLKSEL_MASK (0x7 << 0) -#define EXYNOS4X12_CLKSEL_9600K (0x0 << 0) -#define EXYNOS4X12_CLKSEL_10M (0x1 << 0) -#define EXYNOS4X12_CLKSEL_12M (0x2 << 0) -#define EXYNOS4X12_CLKSEL_19200K (0x3 << 0) -#define EXYNOS4X12_CLKSEL_20M (0x4 << 0) -#define EXYNOS4X12_CLKSEL_24M (0x5 << 0) - -#define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08) -#define HOST_LINK_PORT_SWRST_MASK (0xf << 6) -#define HOST_LINK_PORT2_SWRST (1 << 9) -#define HOST_LINK_PORT1_SWRST (1 << 8) -#define HOST_LINK_PORT0_SWRST (1 << 7) -#define HOST_LINK_ALL_SWRST (1 << 6) - -#define PHY1_SWRST_MASK (0x7 << 3) -#define PHY1_HSIC_SWRST (1 << 5) -#define PHY1_STD_SWRST (1 << 4) -#define PHY1_ALL_SWRST (1 << 3) - -#define PHY0_SWRST_MASK (0x7 << 0) -#define PHY0_PHYLINK_SWRST (1 << 2) -#define PHY0_HLINK_SWRST (1 << 1) -#define PHY0_SWRST (1 << 0) - -#define EXYNOS4_PHY1CON EXYNOS4_HSOTG_PHYREG(0x34) -#define FPENABLEN (1 << 0) - -#endif /* __PLAT_S5P_REGS_USB_PHY_H */