From patchwork Tue Jun 18 14:33:15 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Sharma X-Patchwork-Id: 2742641 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 07B359F3A0 for ; Tue, 18 Jun 2013 14:10:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B757E20435 for ; Tue, 18 Jun 2013 14:09:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 82BEC20373 for ; Tue, 18 Jun 2013 14:09:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932869Ab3FROJs (ORCPT ); Tue, 18 Jun 2013 10:09:48 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:51131 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932855Ab3FROJr (ORCPT ); Tue, 18 Jun 2013 10:09:47 -0400 Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MOL00175E07N890@mailout3.samsung.com> for linux-samsung-soc@vger.kernel.org; Tue, 18 Jun 2013 23:09:47 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.125]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id F4.15.08825.A2A60C15; Tue, 18 Jun 2013 23:09:46 +0900 (KST) X-AuditID: cbfee68e-b7f276d000002279-cb-51c06a2ad2d3 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 09.7F.28381.A2A60C15; Tue, 18 Jun 2013 23:09:46 +0900 (KST) Received: from chromeserver-PowerEdge-T410.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MOL00G19DZTS050@mmp1.samsung.com>; Tue, 18 Jun 2013 23:09:46 +0900 (KST) From: Rahul Sharma To: linux-samsung-soc@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, dri-devel@lists.freedesktop.org Cc: kgene.kim@samsung.com, sw0312.kim@samsung.com, inki.dae@samsung.com, joshi@samsung.com, r.sh.open@gmail.com, Rahul Sharma Subject: [PATCH 2/5] clk/exynos5420: add gate clock for tv sysmmu Date: Tue, 18 Jun 2013 20:03:15 +0530 Message-id: <1371565998-3642-3-git-send-email-rahul.sharma@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1371565998-3642-1-git-send-email-rahul.sharma@samsung.com> References: <1371565998-3642-1-git-send-email-rahul.sharma@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrDLMWRmVeSWpSXmKPExsWyRsSkVlcr60CgQcsza4sDsx+yWlz5+p7N YtL9CSwW33d9YbfoXXCVzWLG+X1MFgtfxFtMWXSY1WLG5JdsDpweO2fdZfe4332cyeP8jIWM Hn1bVjF6fN4kF8AaxWWTkpqTWZZapG+XwJXR+/I4S8Flvort6y4zNzAu5+li5OCQEDCR+LUw qYuRE8gUk7hwbz1bFyMXh5DAUkaJv98OMMPU3J3kClIjJLCIUeLbkVCImtlMEvc2bmMDSbAJ 6ErMPviMEcQWEciVaPjbzgJSxCwwi1Hi++wz7CCDhAUcJc5f1QCpYRFQlbjXMw+sl1fAXaKn 5y8jxBGKEt3PJoDFOQU8JM7dv8EKsdhdYmbnbzaImnXsEtdW80DMEZD4NvkQC8SdshKbQE4G KZGUOLjiBssERuEFjAyrGEVTC5ILipPSi4z0ihNzi0vz0vWS83M3MQJD/vS/Z307GG8esD7E mAw0biKzlGhyPjBm8kriDY3NjCxMTUyNjcwtzUgTVhLnVWuxDhQSSE8sSc1OTS1ILYovKs1J LT7EyMTBKdXAOPO0luOUUJ+qi2qP5U792bz8Y8HRhL2Tt9q8TBX4Y3a4Sqz1Xr3e4e65ilZL pX67POO6lsGc1Vly1W5+9QKzcI+dWjazL/mKZl/cK7uiXvx+p9HTDN3He+ZvmPF9glXujlzG 7YkCkwMlenti3jj72TlcaVl+NGTV5fb57WyJG1JiJARaUz9OV2Ipzkg01GIuKk4EACfIVh2P AgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrNIsWRmVeSWpSXmKPExsVy+t9jAV2trAOBBo0HTCwOzH7IanHl63s2 i0n3J7BYfN/1hd2id8FVNosZ5/cxWSx8EW8xZdFhVosZk1+yOXB67Jx1l93jfvdxJo/zMxYy evRtWcXo8XmTXABrVAOjTUZqYkpqkUJqXnJ+SmZeuq2Sd3C8c7ypmYGhrqGlhbmSQl5ibqqt kotPgK5bZg7QQUoKZYk5pUChgMTiYiV9O0wTQkPcdC1gGiN0fUOC4HqMDNBAwhrGjN6Xx1kK LvNVbF93mbmBcTlPFyMHh4SAicTdSa5djJxAppjEhXvr2UBsIYFFjBLfjoR2MXIB2bOZJO5t 3AaWYBPQlZh98BkjiC0ikCvR8LedBaSIWWAWo8T32WfYQYYKCzhKnL+qAVLDIqAqca9nHlgv r4C7RE/PX0aIZYoS3c8mgMU5BTwkzt2/wQqx2F1iZudvtgmMvAsYGVYxiqYWJBcUJ6XnGuoV J+YWl+al6yXn525iBEfVM6kdjCsbLA4xCnAwKvHwJojtDxRiTSwrrsw9xCjBwawkwquQeCBQ iDclsbIqtSg/vqg0J7X4EGMy0FUTmaVEk/OBEZ9XEm9obGJuamxqaWJhYmZJmrCSOO+BVutA IYH0xJLU7NTUgtQimC1MHJxSDYwu+8yjDyVIz3VdEB6xO491cp/JK5/9UveP296xjpbZOf2J 6buLuRMn3b3SFRKmzeDDEZWav+lxGWf9m4VZM8/PMn74J5pt58Nd+75tKHl261/ixcMX5N++ yOm6uCL0zZLPL+6nqS5zWukl57HQSoyt+5Ygg35V64Ppa5ZY/rLI/ZEcqaaesfCzEktxRqKh FnNRcSIA9FMzau4CAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adding sysmmu clock for tv for exynos5420. Signed-off-by: Rahul Sharma --- Documentation/devicetree/bindings/clock/exynos5420-clock.txt | 1 + drivers/clk/samsung/clk-exynos5420.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt index 596a368..f0b1ce0 100644 --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt @@ -180,6 +180,7 @@ clock which they consume. fimc_lite3 495 aclk_g3d 500 g3d 501 + smmu_tv 502 Example 1: An example of a clock controller node is listed below. diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 0945435..e8be481 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -109,7 +109,7 @@ enum exynos5420_clks { aclk300_gscl = 460, smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0, gscl1, clk_3aa, aclk266_g2d = 470, sss, slim_sss, mdma0, aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0, - smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, + smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, smmu_tv, nr_clks, }; @@ -696,6 +696,7 @@ struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { GATE(smmu_mscl0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0, 0), GATE(smmu_mscl1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0, 0), GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0), + GATE(smmu_tv, "smmu_tv", "aclk200_disp1", GATE_IP_DISP1, 9, 0, 0), }; static __initdata struct of_device_id ext_clk_match[] = {