From patchwork Wed Jun 26 10:13:45 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartlomiej Zolnierkiewicz X-Patchwork-Id: 2783771 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A079AC0AB1 for ; Wed, 26 Jun 2013 10:14:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 176E92040A for ; Wed, 26 Jun 2013 10:14:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 998F7203F8 for ; Wed, 26 Jun 2013 10:14:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752027Ab3FZKOU (ORCPT ); Wed, 26 Jun 2013 06:14:20 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:15082 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751937Ab3FZKOS (ORCPT ); Wed, 26 Jun 2013 06:14:18 -0400 Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MOZ00KOQWF7BDW0@mailout4.samsung.com>; Wed, 26 Jun 2013 19:14:17 +0900 (KST) X-AuditID: cbfee61b-b7f8e6d00000524c-1c-51cabef92656 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id A8.63.21068.9FEBAC15; Wed, 26 Jun 2013 19:14:17 +0900 (KST) Received: from mcdsrvbld02.digital.local ([106.116.37.23]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MOZ0076CWFFZO80@mmp1.samsung.com>; Wed, 26 Jun 2013 19:14:17 +0900 (KST) From: Bartlomiej Zolnierkiewicz To: kgene.kim@samsung.com Cc: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, jc.lee@samsung.com, lorenzo.pieralisi@arm.com, amit.kachhap@linaro.org, t.figa@samsung.com, daniel.lezcano@linaro.org, rjw@sisk.pl, kyungmin.park@samsung.com, b.zolnierkie@samsung.com Subject: [PATCH 1/3] ARM: EXYNOS: remove non-working AFTR mode support Date: Wed, 26 Jun 2013 12:13:45 +0200 Message-id: <1372241627-22695-2-git-send-email-b.zolnierkie@samsung.com> X-Mailer: git-send-email 1.7.10 In-reply-to: <1372241627-22695-1-git-send-email-b.zolnierkie@samsung.com> References: <1372241627-22695-1-git-send-email-b.zolnierkie@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrHLMWRmVeSWpSXmKPExsVy+t9jAd2f+04FGvzcoWCx5MEURouNM9az Wsz7LGsx8cM9RoveBVfZLM42vWG32PT4GqvF594jjBYzzu9jsnjz+wW7Rf/CXiaL9TNeszjw eKyZt4bR4861PWwem5fUe/RtWcXo8WhxC6PH501yAWxRXDYpqTmZZalF+nYJXBmPd09hL1ht UPHz/Ve2BsbT6l2MnBwSAiYSx+5PYIawxSQu3FvPBmILCSxilDjySa6LkQvI7mKSmHnpHDtI gk3ASmJi+ypGEFtEQFKiqeEPWDOzwBImib1ba0FsYQE3iVXz9wHFOThYBFQlXq5UBgnzCnhI NGxcCrVLXuLp/T6wXZwCnhKLNi1ghtjrIbHiyHvmCYy8CxgZVjGKphYkFxQnpeca6RUn5haX 5qXrJefnbmIEh+Iz6R2MqxosDjEKcDAq8fAqbD0ZKMSaWFZcmXuIUYKDWUmE9838U4FCvCmJ lVWpRfnxRaU5qcWHGKU5WJTEeQ+2WgcKCaQnlqRmp6YWpBbBZJk4OKUaGJm+hJSUagWYvGTe G1Osqbpbjpf956affziLnjvdlNjw+7pKspbdMXXf+ketso9n8F37FRHwzVVt/r1FCROy5j1/ M72ntrFKtitj95OEEJc1i39lyOs837l086bJHv93F/79UhjhkZXhekpzk9/TnZLi3ttfFIvr uXcvd9HQWfVvaubXgl+fypRYijMSDbWYi4oTAdTkpoxBAgAA Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP AFTR mode support was introduced by commit 67173ca ("ARM: EXYNOS: Add support AFTR mode on EXYNOS4210") in v3.4 kernel. Unfortunately even in v3.4 kernel it hasn't worked as supposed and this is still the case with v3.10-rc6 (it probably wasn't noticed because CONFIG_CPU_IDLE is not turned on by default): - on revision 0 of Exynos4210 (Universal C210 board) it causes lockup (on this revision only one core is usable so entry to AFTR mode is always attempted because the code tries to go into AFTR mode when all other CPUs except CPU0 are offlined) - on revision 1.1 of Exynos4210 (Trats board) it causes a lockup when CPU1 is offlined (i.e. echo 0 > /sys/devices/system/cpu/cpu1/online) - on later Exynos4/5 SoCs wrong registers may be accessed when all CPUs except CPU0 are offlined resulting in panic/lockup (REG_DIRECTGO_ADDR and REG_DIRECTGO_FLAG register selections was implemented only for Exynos4210) Just remove AFTR mode support for now. Cc: Jaecheol Lee Cc: Lorenzo Pieralisi Cc: Amit Daniel Kachhap Cc: Tomasz Figa Cc: Kukjin Kim Cc: Daniel Lezcano Cc: "Rafael J. Wysocki" Signed-off-by: Kyungmin Park Signed-off-by: Bartlomiej Zolnierkiewicz --- arch/arm/mach-exynos/cpuidle.c | 131 +---------------------------------------- 1 file changed, 1 insertion(+), 130 deletions(-) diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c index 17a18ff..0a657ac 100644 --- a/arch/arm/mach-exynos/cpuidle.c +++ b/arch/arm/mach-exynos/cpuidle.c @@ -17,30 +17,11 @@ #include #include -#include -#include -#include #include #include -#include - -#include #include "common.h" -#define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \ - S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ - (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0)) -#define REG_DIRECTGO_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ - S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ - (S5P_VA_SYSRAM + 0x20) : S5P_INFORM1)) - -#define S5P_CHECK_AFTR 0xFCBA0D10 - -static int exynos4_enter_lowpower(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index); - static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device); static struct cpuidle_driver exynos4_idle_driver = { @@ -48,117 +29,11 @@ static struct cpuidle_driver exynos4_idle_driver = { .owner = THIS_MODULE, .states = { [0] = ARM_CPUIDLE_WFI_STATE, - [1] = { - .enter = exynos4_enter_lowpower, - .exit_latency = 300, - .target_residency = 100000, - .flags = CPUIDLE_FLAG_TIME_VALID, - .name = "C1", - .desc = "ARM power down", - }, }, - .state_count = 2, + .state_count = 1, .safe_state_index = 0, }; -/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */ -static void exynos4_set_wakeupmask(void) -{ - __raw_writel(0x0000ff3e, S5P_WAKEUP_MASK); -} - -static unsigned int g_pwr_ctrl, g_diag_reg; - -static void save_cpu_arch_register(void) -{ - /*read power control register*/ - asm("mrc p15, 0, %0, c15, c0, 0" : "=r"(g_pwr_ctrl) : : "cc"); - /*read diagnostic register*/ - asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc"); - return; -} - -static void restore_cpu_arch_register(void) -{ - /*write power control register*/ - asm("mcr p15, 0, %0, c15, c0, 0" : : "r"(g_pwr_ctrl) : "cc"); - /*write diagnostic register*/ - asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc"); - return; -} - -static int idle_finisher(unsigned long flags) -{ - cpu_do_idle(); - return 1; -} - -static int exynos4_enter_core0_aftr(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - unsigned long tmp; - - exynos4_set_wakeupmask(); - - /* Set value of power down register for aftr mode */ - exynos_sys_powerdown_conf(SYS_AFTR); - - __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR); - __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG); - - save_cpu_arch_register(); - - /* Setting Central Sequence Register for power down mode */ - tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); - tmp &= ~S5P_CENTRAL_LOWPWR_CFG; - __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); - - cpu_pm_enter(); - cpu_suspend(0, idle_finisher); - -#ifdef CONFIG_SMP - if (!soc_is_exynos5250()) - scu_enable(S5P_VA_SCU); -#endif - cpu_pm_exit(); - - restore_cpu_arch_register(); - - /* - * If PMU failed while entering sleep mode, WFI will be - * ignored by PMU and then exiting cpu_do_idle(). - * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically - * in this situation. - */ - tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); - if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { - tmp |= S5P_CENTRAL_LOWPWR_CFG; - __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); - } - - /* Clear wakeup state register */ - __raw_writel(0x0, S5P_WAKEUP_STAT); - - return index; -} - -static int exynos4_enter_lowpower(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - int new_index = index; - - /* This mode only can be entered when other core's are offline */ - if (num_online_cpus() > 1) - new_index = drv->safe_state_index; - - if (new_index == 0) - return arm_cpuidle_simple_enter(dev, drv, new_index); - else - return exynos4_enter_core0_aftr(dev, drv, new_index); -} - static void __init exynos5_core_down_clk(void) { unsigned int tmp; @@ -209,10 +84,6 @@ static int __init exynos4_init_cpuidle(void) device = &per_cpu(exynos4_cpuidle_device, cpu_id); device->cpu = cpu_id; - /* Support IDLE only */ - if (cpu_id != 0) - device->state_count = 1; - ret = cpuidle_register_device(device); if (ret) { printk(KERN_ERR "CPUidle register device failed\n");