From patchwork Wed Jul 10 12:11:51 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Padmavathi Venna X-Patchwork-Id: 2825649 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D80DFC0AB3 for ; Wed, 10 Jul 2013 12:06:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9F82A201BB for ; Wed, 10 Jul 2013 12:06:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B0B43201BE for ; Wed, 10 Jul 2013 12:06:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754095Ab3GJMGn (ORCPT ); Wed, 10 Jul 2013 08:06:43 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:17984 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751173Ab3GJMGn (ORCPT ); Wed, 10 Jul 2013 08:06:43 -0400 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MPP00DGFYZ5M640@mailout2.samsung.com> for linux-samsung-soc@vger.kernel.org; Wed, 10 Jul 2013 21:06:42 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.122]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id BD.EA.03969.15E4DD15; Wed, 10 Jul 2013 21:06:41 +0900 (KST) X-AuditID: cbfee68f-b7f436d000000f81-2e-51dd4e51e88e Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id C4.0A.28381.15E4DD15; Wed, 10 Jul 2013 21:06:41 +0900 (KST) Received: from padma-linuxpc.sisodomain.com ([107.108.83.35]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MPP0018RYYV9N30@mmp2.samsung.com>; Wed, 10 Jul 2013 21:06:41 +0900 (KST) From: Padmavathi Venna To: linux-samsung-soc@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, alsa-devel@alsa-project.org, padma.v@samsung.com, padma.kvr@gmail.com Cc: sbkim73@samsung.com, broonie@kernel.org, kgene.kim@samsung.com, mturquette@linaro.org, dianders@chromium.org, abrestic@chromium.org Subject: [PATCH 2/4] clk: exynos-audss: allow input clocks to be specified in device tree Date: Wed, 10 Jul 2013 17:41:51 +0530 Message-id: <1373458313-18970-3-git-send-email-padma.v@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1373458313-18970-1-git-send-email-padma.v@samsung.com> References: <1373458313-18970-1-git-send-email-padma.v@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrMIsWRmVeSWpSXmKPExsWyRsSkSjfQ726gQfM/PYuV7/8yWly5eIjJ YurDJ2wWB2Y/ZLU4u+wgm0XvgqtsFpseX2O1mHF+H5PF0wkX2Szal81htfh98zubxcUVX5gc eDw2fG5i85jdcJHFY+esu+wem1Z1snncubaHzWPzknqP8zMWMnr0bVnF6PF5k1wAZxSXTUpq TmZZapG+XQJXRs/Jp0wF2zUqll/axd7AOEuxi5GTQ0LAROL8rVUsELaYxIV769m6GLk4hASW MkpsP/mbFaZo/psljBCJ6YwSMx/tY4Jwepgk7ky5B1TFwcEmoCPRctYFpEFEYDejRO9FC5Aa ZoFORom+U0fYQBLCAtESdzYcA1vHIqAq8eL/bUYQm1fAWaKzq4MJYpuCxLGpX8E2cwq4SPxr fQtWIwRUM/HTdHaQoRICj9glfjx6zQwxSEDi2+RDLCBHSAjISmw6wAwxR1Li4IobLBMYhRcw MqxiFE0tSC4oTkovMtYrTswtLs1L10vOz93ECIyg0/+e9e9gvHvA+hBjMtC4icxSosn5wAjM K4k3NDYzsjA1MTU2Mrc0I01YSZxXrcU6UEggPbEkNTs1tSC1KL6oNCe1+BAjEwenVANjtOrB +XP2xO6yeG94bFvdN4MPUz7tmfT+yO3rR1U/zeU8Zc/O9WP9o5QruyRfJzI/nen8+YSd42rr B6dnzbFiu/ZU+GHWNca46vB9P9fHZC71Yz+zI8b7leLp9I2fjDYqcLyRUnBf/+3TbefJO76t 1687cOXyjmmpezx5JXpN6jJSV5WH2bX8dVViKc5INNRiLipOBAAXqdEttgIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpgleLIzCtJLcpLzFFi42I5/e+xoG6g391Ag/WPFC1Wvv/LaHHl4iEm i6kPn7BZHJj9kNXi7LKDbBa9C66yWWx6fI3VYsb5fUwWTydcZLNoXzaH1eL3ze9sFhdXfGFy 4PHY8LmJzWN2w0UWj52z7rJ7bFrVyeZx59oeNo/NS+o9zs9YyOjRt2UVo8fnTXIBnFENjDYZ qYkpqUUKqXnJ+SmZeem2St7B8c7xpmYGhrqGlhbmSgp5ibmptkouPgG6bpk5QDcrKZQl5pQC hQISi4uV9O0wTQgNcdO1gGmM0PUNCYLrMTJAAwlrGDN6Tj5lKtiuUbH80i72BsZZil2MnBwS AiYS898sYYSwxSQu3FvP1sXIxSEkMJ1RYuajfUwQTg+TxJ0p91i7GDk42AR0JFrOuoA0iAjs ZpTovWgBUsMs0Mko0XfqCBtIQlggWuLOhmMsIDaLgKrEi/+3wTbwCjhLdHZ1MEFsU5A4NvUr K4jNKeAi8a/1LViNEFDNxE/T2Scw8i5gZFjFKJpakFxQnJSea6hXnJhbXJqXrpecn7uJERyf z6R2MK5ssDjEKMDBqMTDe0DhTqAQa2JZcWXuIUYJDmYlEV51q7uBQrwpiZVVqUX58UWlOanF hxiTga6ayCwlmpwPTB15JfGGxibmpsamliYWJmaWpAkrifMeaLUOFBJITyxJzU5NLUgtgtnC xMEp1cBYE2h9SGZTSYX//g81XNq35wWJCBlzT/tY/OnT+YWSAr93zH6wy633UUiZ9XmpA6t7 Uy58n7ojzEF8cqaZzek7fC+CxNcuijqu/DBA4dnqmglt/urPZ348eUhj8/yTPWoa3I4flkaG 6B7asCCv88eWTjOXPH/r+Zbu7ev19jZLlDy/dNIjNKtWiaU4I9FQi7moOBEA/zaEZhMDAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Andrew Bresticker This allows the input clocks to the Exynos AudioSS block to be specified via device-tree bindings. Default names will be used when an input clock is not given. This will be useful when adding support for the Exynos5420 where the audio bus clock is called "sclk_maudio0" instead of "sclk_audio0". Signed-off-by: Andrew Bresticker Reviewed-on: https://gerrit.chromium.org/gerrit/57833 Reviewed-by: Simon Glass --- .../devicetree/bindings/clock/clk-exynos-audss.txt | 31 ++++++++++++++++++- drivers/clk/samsung/clk-exynos-audss.c | 28 +++++++++++++++-- 2 files changed, 53 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt index 3115930..66d4662 100644 --- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt +++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt @@ -16,6 +16,21 @@ Required Properties: - #clock-cells: should be 1. +Optional Properties: + +- clocks: + - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" + is used if not specified. + - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" + is used if not specified. + - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not + specified. + - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if + not specified. + +- clock-names: Aliases for the above clocks. They should be "pll_ref", + "pll_in", "cdclk", and "sclk_audio", respectively. + The following is the list of clocks generated by the controller. Each clock is assigned an identifier and client nodes use this identifier to specify the clock which they consume. Some of the clocks are available only on a particular @@ -38,15 +53,27 @@ pcm_bus 8 sclk_pcm 9 adma 10 Exynos5420 -Example 1: An example of a clock controller node is listed below. +Example 1: An example of a clock controller node using the default input + clock names is listed below. + +clock_audss: audss-clock-controller@3810000 { + compatible = "samsung,exynos5250-audss-clock"; + reg = <0x03810000 0x0C>; + #clock-cells = <1>; +}; + +Example 2: An example of a clock controller node with audio bus input clock + specified is listed below. clock_audss: audss-clock-controller@3810000 { compatible = "samsung,exynos5250-audss-clock"; reg = <0x03810000 0x0C>; #clock-cells = <1>; + clocks = <&clock 148>; + clock-names = "sclk_audio"; }; -Example 2: I2S controller node that consumes the clock generated by the clock +Example 3: I2S controller node that consumes the clock generated by the clock controller. Refer to the standard clock bindings for information about 'clocks' and 'clock-names' property. diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index 86d2606..39d3383 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -32,10 +32,6 @@ static unsigned long reg_save[][2] = { {ASS_CLK_GATE, 0}, }; -/* list of all parent clock list */ -static const char *mout_audss_p[] = { "fin_pll", "fout_epll" }; -static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" }; - #ifdef CONFIG_PM_SLEEP static int exynos_audss_clk_suspend(void) { @@ -64,6 +60,10 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = { /* register exynos_audss clocks */ void __init exynos_audss_clk_init(struct device_node *np) { + const char *mout_audss_p[] = {"fin_pll", "fout_epll"}; + const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"}; + struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio; + reg_base = of_iomap(np, 0); if (!reg_base) { pr_err("%s: failed to map audss registers\n", __func__); @@ -81,10 +81,30 @@ void __init exynos_audss_clk_init(struct device_node *np) clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS; of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + pll_ref = of_clk_get_by_name(np, "pll_ref"); + pll_in = of_clk_get_by_name(np, "pll_in"); + if (!IS_ERR(pll_ref)) { + mout_audss_p[0] = __clk_get_name(pll_ref); + clk_put(pll_ref); + } + if (!IS_ERR(pll_in)) { + mout_audss_p[1] = __clk_get_name(pll_in); + clk_put(pll_in); + } clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss", mout_audss_p, ARRAY_SIZE(mout_audss_p), 0, reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); + cdclk = of_clk_get_by_name(np, "cdclk"); + sclk_audio = of_clk_get_by_name(np, "sclk_audio"); + if (!IS_ERR(cdclk)) { + mout_i2s_p[1] = __clk_get_name(cdclk); + clk_put(cdclk); + } + if (!IS_ERR(sclk_audio)) { + mout_i2s_p[2] = __clk_get_name(sclk_audio); + clk_put(sclk_audio); + } clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s", mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 0, reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);