From patchwork Tue Aug 6 08:34:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 2839245 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 5C9BEBF535 for ; Tue, 6 Aug 2013 08:35:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5251220149 for ; Tue, 6 Aug 2013 08:35:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EA5592017B for ; Tue, 6 Aug 2013 08:35:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753591Ab3HFIfB (ORCPT ); Tue, 6 Aug 2013 04:35:01 -0400 Received: from mail-pd0-f176.google.com ([209.85.192.176]:35489 "EHLO mail-pd0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753526Ab3HFIe7 (ORCPT ); Tue, 6 Aug 2013 04:34:59 -0400 Received: by mail-pd0-f176.google.com with SMTP id q10so92363pdj.35 for ; Tue, 06 Aug 2013 01:34:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zbOWG9VisgQnKiHXnkVFXMzi+Db+g29AOk/29e1X6Qw=; b=NiWGrcvWXXiP7E6rbfR/Cq77LEzdpj9Bcbd1qZbiO/Y9P+U78ygU9qxAHOgHRW5fe5 rBSdW9P6+bTGUOjk/dybm15SJH7kW1w9O6TZMaRr1dEW/2+1//xH+5xRfM2uXAdpFs0l HljjE5Y8Ta60ieq8uHkzX6/VrZPDFqU8/zhoG4LC1xOyoyExxByVGTDn9e6Un9DhJJj1 frl/mBJQebRkvhTMLMnEaGNfd1XtBzXn6LtVfazHHxP0tzqBz2egGHr7nnkcqPRSnC8v ZRPGzuNvsy/xmKHOuxOgsX6ko4soaY4bgMFf3tSUOuVa/TTJjEkq7IP3Dpvz6jrJ7PeI v1Jw== X-Gm-Message-State: ALoCoQmAFIKCWZJgvsmk7+QmOQgY3cRWgvjrAT09kChJBmv3GNIchRCpAEzsUEo8DgRG304Olrk9 X-Received: by 10.68.253.138 with SMTP id aa10mr314414pbd.24.1375778098365; Tue, 06 Aug 2013 01:34:58 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id wr9sm621435pbc.7.2013.08.06.01.34.55 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 06 Aug 2013 01:34:57 -0700 (PDT) From: Chander Kashyap To: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org, mturquette@linaro.org, thomas.abraham@linaro.org, Chander Kashyap Subject: [RFC PATCH 1/3] clk: add support for temporary parent clock migration Date: Tue, 6 Aug 2013 14:04:23 +0530 Message-Id: <1375778065-21808-2-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1375778065-21808-1-git-send-email-chander.kashyap@linaro.org> References: <1375778065-21808-1-git-send-email-chander.kashyap@linaro.org> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some platforms use to migrate temporarily to another parent during cpu frequency scaling, e.g. Exynos and Tegra. Once the frequency is changed the latch on to original parent. The generic cpufreq-cpu0 driver use CCF to scale cpu frequency. This patch is an attempt to address the above mentioned requirement. This is achieved as follows: Add a clk flag "CLK_SET_RATE_ALTERNATE" for clocks which need to migrate to another parent during set_rate operation on them. Add "alternate_parent_name" and "alternate_parent" fields to clk structure i.e the name of alternate_parent_clock and reference to alternate_parent_clock. Hence in clk_set_rate API check for the "CLK_SET_RATE_ALTERNATE" flag, then latch on to alternate parent clock temporarily. Once the requested rate is set on the clk, re-parent back to original parent clock. This property is applicable only for mux-clocks, where it is guaranteed that set_rate will actually execute on parent clock. Signed-off-by: Chander Kashyap --- drivers/clk/clk-mux.c | 13 ++++++------ drivers/clk/clk.c | 45 +++++++++++++++++++++++++++++++++++++++--- include/linux/clk-private.h | 17 +++++++++------- include/linux/clk-provider.h | 10 ++++++---- 4 files changed, 65 insertions(+), 20 deletions(-) diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 614444c..47cb77f 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -109,8 +109,8 @@ EXPORT_SYMBOL_GPL(clk_mux_ops); struct clk *clk_register_mux_table(struct device *dev, const char *name, const char **parent_names, u8 num_parents, unsigned long flags, - void __iomem *reg, u8 shift, u32 mask, - u8 clk_mux_flags, u32 *table, spinlock_t *lock) + const char *alternate_parent_name, void __iomem *reg, u8 shift, + u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock) { struct clk_mux *mux; struct clk *clk; @@ -137,6 +137,7 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name, init.flags = flags | CLK_IS_BASIC; init.parent_names = parent_names; init.num_parents = num_parents; + init.alternate_parent_name = alternate_parent_name; /* struct clk_mux assignments */ mux->reg = reg; @@ -157,12 +158,12 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name, struct clk *clk_register_mux(struct device *dev, const char *name, const char **parent_names, u8 num_parents, unsigned long flags, - void __iomem *reg, u8 shift, u8 width, - u8 clk_mux_flags, spinlock_t *lock) + const char *alternate_parent_name, void __iomem *reg, u8 shift, + u8 width, u8 clk_mux_flags, spinlock_t *lock) { u32 mask = BIT(width) - 1; return clk_register_mux_table(dev, name, parent_names, num_parents, - flags, reg, shift, mask, clk_mux_flags, - NULL, lock); + flags, alternate_parent_name, reg, shift, + mask, clk_mux_flags, NULL, lock); } diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 54a191c..0f18a45 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -1209,8 +1209,8 @@ static void clk_change_rate(struct clk *clk) */ int clk_set_rate(struct clk *clk, unsigned long rate) { - struct clk *top, *fail_clk; - int ret = 0; + struct clk *top, *fail_clk, *parent = NULL; + int ret = 0, index; /* prevent racing with updates to the clock topology */ clk_prepare_lock(); @@ -1231,6 +1231,36 @@ int clk_set_rate(struct clk *clk, unsigned long rate) goto out; } + /* Latch on to alternate parent temporarily if needed */ + if ((clk->flags & CLK_SET_RATE_ALTERNATE) + && clk->alternate_parent_name) { + /* Save current parent before latching on to alternate parent */ + parent = clk->parent; + + if (!clk->alternate_parent) { + for (index = 0; index < clk->num_parents; index++) { + if (!strcmp(clk->parent_names[index], + clk->alternate_parent_name)) + clk->alternate_parent = + __clk_lookup(clk->alternate_parent_name); + } + + if (!clk->alternate_parent) { + pr_warn("%s: wrong alternate_parent_name %s", + __func__, clk->alternate_parent_name); + ret = -EINVAL; + goto out; + } + } + + ret = clk_set_parent(clk, clk->alternate_parent); + if (ret) { + pr_warn("%s: failed to set %s parent\n", + __func__, clk->alternate_parent->name); + goto out; + } + } + /* notify that we are about to change rates */ fail_clk = clk_propagate_rate_change(top, PRE_RATE_CHANGE); if (fail_clk) { @@ -1243,8 +1273,15 @@ int clk_set_rate(struct clk *clk, unsigned long rate) /* change the rates */ clk_change_rate(top); - out: + /* Reparent back to original parent */ + if (parent) { + ret = clk_set_parent(clk, parent); + if (ret) + pr_warn("%s: failed to set %s parent\n", + __func__, parent->name); + } + clk_prepare_unlock(); return ret; @@ -1690,6 +1727,7 @@ struct clk *__clk_register(struct device *dev, struct clk_hw *hw) clk->flags = hw->init->flags; clk->parent_names = hw->init->parent_names; clk->num_parents = hw->init->num_parents; + clk->alternate_parent_name = hw->init->alternate_parent_name; ret = __clk_init(dev, clk); if (ret) @@ -1713,6 +1751,7 @@ static int _clk_register(struct device *dev, struct clk_hw *hw, struct clk *clk) clk->hw = hw; clk->flags = hw->init->flags; clk->num_parents = hw->init->num_parents; + clk->alternate_parent_name = hw->init->alternate_parent_name; hw->clk = clk; /* allocate local copy in case parent_names is __initdata */ diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h index dd7adff..f295af0 100644 --- a/include/linux/clk-private.h +++ b/include/linux/clk-private.h @@ -44,6 +44,8 @@ struct clk { #ifdef CONFIG_COMMON_CLK_DEBUG struct dentry *dentry; #endif + const char *alternate_parent_name; + struct clk *alternate_parent; }; /* @@ -56,7 +58,7 @@ struct clk { */ #define DEFINE_CLK(_name, _ops, _flags, _parent_names, \ - _parents) \ + _parents, _alternate_parent_name) \ static struct clk _name = { \ .name = #_name, \ .ops = &_ops, \ @@ -65,6 +67,7 @@ struct clk { .num_parents = ARRAY_SIZE(_parent_names), \ .parents = _parents, \ .flags = _flags | CLK_IS_BASIC, \ + .alternate_parent_name = _alternate_parent_name \ } #define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate, \ @@ -79,7 +82,7 @@ struct clk { .flags = _fixed_rate_flags, \ }; \ DEFINE_CLK(_name, clk_fixed_rate_ops, _flags, \ - _name##_parent_names, NULL); + _name##_parent_names, NULL, NULL); #define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr, \ _flags, _reg, _bit_idx, \ @@ -101,7 +104,7 @@ struct clk { .lock = _lock, \ }; \ DEFINE_CLK(_name, clk_gate_ops, _flags, \ - _name##_parent_names, _name##_parents); + _name##_parent_names, _name##_parents, NULL); #define _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \ _flags, _reg, _shift, _width, \ @@ -125,7 +128,7 @@ struct clk { .lock = _lock, \ }; \ DEFINE_CLK(_name, clk_divider_ops, _flags, \ - _name##_parent_names, _name##_parents); + _name##_parent_names, _name##_parents, NULL); #define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \ _flags, _reg, _shift, _width, \ @@ -143,8 +146,8 @@ struct clk { _divider_flags, _table, _lock) \ #define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, \ - _reg, _shift, _width, \ - _mux_flags, _lock) \ + _alternate_parent_name, _reg, \ + _shift, _width, _mux_flags, _lock) \ static struct clk _name; \ static struct clk_mux _name##_hw = { \ .hw = { \ @@ -157,7 +160,7 @@ struct clk { .lock = _lock, \ }; \ DEFINE_CLK(_name, clk_mux_ops, _flags, _parent_names, \ - _parents); + _parents, _alternate_parentn_name); #define DEFINE_CLK_FIXED_FACTOR(_name, _parent_name, \ _parent_ptr, _flags, \ diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 1ec14a7..25071b5 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -27,6 +27,7 @@ #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ +#define CLK_SET_RATE_ALTERNATE BIT(7) /* migrate to alternate parent */ struct clk_hw; @@ -149,6 +150,7 @@ struct clk_init_data { const char **parent_names; u8 num_parents; unsigned long flags; + const char *alternate_parent_name; }; /** @@ -332,13 +334,13 @@ extern const struct clk_ops clk_mux_ops; struct clk *clk_register_mux(struct device *dev, const char *name, const char **parent_names, u8 num_parents, unsigned long flags, - void __iomem *reg, u8 shift, u8 width, - u8 clk_mux_flags, spinlock_t *lock); + const char *alternate_parent_name, void __iomem *reg, u8 shift, + u8 width, u8 clk_mux_flags, spinlock_t *lock); struct clk *clk_register_mux_table(struct device *dev, const char *name, const char **parent_names, u8 num_parents, unsigned long flags, - void __iomem *reg, u8 shift, u32 mask, - u8 clk_mux_flags, u32 *table, spinlock_t *lock); + const char *alternate_parent_name, void __iomem *reg, u8 shift, + u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock); void of_fixed_factor_clk_setup(struct device_node *node);