From patchwork Tue Aug 20 17:31:38 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 2847214 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B1A449F239 for ; Tue, 20 Aug 2013 17:32:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6610720451 for ; Tue, 20 Aug 2013 17:32:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E0A8120549 for ; Tue, 20 Aug 2013 17:32:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751853Ab3HTRcO (ORCPT ); Tue, 20 Aug 2013 13:32:14 -0400 Received: from mailout3.w1.samsung.com ([210.118.77.13]:41640 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751428Ab3HTRcH (ORCPT ); Tue, 20 Aug 2013 13:32:07 -0400 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout3.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MRU0051UBD7UJE0@mailout3.w1.samsung.com>; Tue, 20 Aug 2013 18:32:06 +0100 (BST) X-AuditID: cbfec7f5-b7f5f6d00000105f-b7-5213a816f9c7 Received: from eusync3.samsung.com ( [203.254.199.213]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id BF.24.04191.618A3125; Tue, 20 Aug 2013 18:32:06 +0100 (BST) Received: from amdc1227.digital.local ([106.116.147.199]) by eusync3.samsung.com (Oracle Communications Messaging Server 7u4-23.01(7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0MRU00779BD55310@eusync3.samsung.com>; Tue, 20 Aug 2013 18:32:06 +0100 (BST) From: Tomasz Figa To: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, Kukjin Kim , Mike Turquette , Daniel Lezcano , Mark Rutland , Pawel Moll , Rob Herring , Stephen Warren , Thomas Abraham , Thomas Gleixner , Tushar Behera , Yadwinder Singh Brar , Doug Anderson , Kumar Gala , Tomasz Figa , Kyungmin Park Subject: [PATCH 11/16] clk: samsung: pll: Use new registration method for PLL46xx Date: Tue, 20 Aug 2013 19:31:38 +0200 Message-id: <1377019903-14614-12-git-send-email-t.figa@samsung.com> X-Mailer: git-send-email 1.8.3.2 In-reply-to: <1377019903-14614-1-git-send-email-t.figa@samsung.com> References: <1377019903-14614-1-git-send-email-t.figa@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrMLMWRmVeSWpSXmKPExsVy+t/xq7piK4SDDJ70ClrM+yxrMf/IOVaL s8sOsln0v1nIatG74CqbxdmmN+wWmx5fY7WYcX4fk8XS6xeZLJ5OuMhmMWH6WhaLwysOMFm8 OtjGYrF+xmsWi82bpjJbHJuxhNGi/e9eNos5098xOQh5rJm3htFjwecr7B6zGy6yeFzu62Xy uHNtD5vHu3Pn2D02L6n36NuyitHj8yY5j41zQwO4orhsUlJzMstSi/TtErgy+m63MRd81Kx4 0vGPqYHxnFIXIyeHhICJxIoZe9khbDGJC/fWs3UxcnEICSxllDh+ajojhNPHJPFs7TpWkCo2 ATWJzw2P2EBsEQENiSldj9lBipgFFrNK3Lr4khEkISwQLHH06jKwsSwCqhIT+9czdTFycPAK OEs0H5CH2KYgsezLWmYQmxMovGHRUrD5QgJOEp37FrFNYORdwMiwilE0tTS5oDgpPddIrzgx t7g0L10vOT93EyMk4L/uYFx6zOoQowAHoxIPL0eJcJAQa2JZcWXuIUYJDmYlEd5tGUAh3pTE yqrUovz4otKc1OJDjEwcnFINjH1MB7dllSom/eJWUXisefRFt8O+33bXNp/dU2L//FJE351p vo78sw/dvdyp+umL1p1MuRBZr/m8GQtK9AMKEnx1VfyOrlhUzSa8SkXvB2OS6NaAF7c8eScI OVTlPWy/xdr9YOfORY8/f+HvK3w5S6mh9UrV79xTYl5XL+2Tq9aqfOZ8N/aSghJLcUaioRZz UXEiANq1g9dWAgAA Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch modifies PLL46xx support code and its users to use the recently introduced common PLL registration helper. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park --- drivers/clk/samsung/clk-exynos4.c | 13 +++------- drivers/clk/samsung/clk-pll.c | 52 +++++---------------------------------- drivers/clk/samsung/clk-pll.h | 14 +++-------- 3 files changed, 14 insertions(+), 65 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 6036fdf..42a4001 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -994,6 +994,10 @@ static struct __initdata samsung_pll_clock exynos4210_plls[nr_plls] = { APLL_CON0, "fout_apll", NULL), [mpll] = PLL_A(pll_4508, fout_mpll, "fout_mpll", "fin_pll", E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL), + [epll] = PLL_A(pll_4600, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK, + EPLL_CON0, "fout_epll", NULL), + [vpll] = PLL_A(pll_4650c, fout_vpll, "fout_vpll", "mout_vpllsrc", + VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL), }; static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { @@ -1012,8 +1016,6 @@ static void __init exynos4_clk_init(struct device_node *np, enum exynos4_soc exynos4_soc, void __iomem *reg_base, unsigned long xom) { - struct clk *epll, *vpll; - reg_base = of_iomap(np, 0); if (!reg_base) panic("%s: failed to map registers\n", __func__); @@ -1036,13 +1038,6 @@ static void __init exynos4_clk_init(struct device_node *np, if (exynos4_soc == EXYNOS4210) { samsung_clk_register_pll(exynos4210_plls, ARRAY_SIZE(exynos4210_plls), reg_base); - epll = samsung_clk_register_pll46xx("fout_epll", "fin_pll", - reg_base + EPLL_CON0, pll_4600); - vpll = samsung_clk_register_pll46xx("fout_vpll", "mout_vpllsrc", - reg_base + VPLL_CON0, pll_4650c); - - samsung_clk_add_lookup(epll, fout_epll); - samsung_clk_add_lookup(vpll, fout_vpll); } else { samsung_clk_register_pll(exynos4x12_plls, ARRAY_SIZE(exynos4x12_plls), reg_base); diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index cb971cb..8a008ca 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -422,18 +422,10 @@ static const struct clk_ops samsung_pll45xx_clk_min_ops = { #define PLL4650C_KDIV_MASK (0xFFF) #define PLL46XX_KDIV_SHIFT (0) -struct samsung_clk_pll46xx { - struct clk_hw hw; - enum pll46xx_type type; - const void __iomem *con_reg; -}; - -#define to_clk_pll46xx(_hw) container_of(_hw, struct samsung_clk_pll46xx, hw) - static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct samsung_clk_pll46xx *pll = to_clk_pll46xx(hw); + struct samsung_clk_pll *pll = to_clk_pll(hw); u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift; u64 fvco = parent_rate; @@ -457,43 +449,6 @@ static const struct clk_ops samsung_pll46xx_clk_ops = { .recalc_rate = samsung_pll46xx_recalc_rate, }; -struct clk * __init samsung_clk_register_pll46xx(const char *name, - const char *pname, const void __iomem *con_reg, - enum pll46xx_type type) -{ - struct samsung_clk_pll46xx *pll; - struct clk *clk; - struct clk_init_data init; - - pll = kzalloc(sizeof(*pll), GFP_KERNEL); - if (!pll) { - pr_err("%s: could not allocate pll clk %s\n", __func__, name); - return NULL; - } - - init.name = name; - init.ops = &samsung_pll46xx_clk_ops; - init.flags = CLK_GET_RATE_NOCACHE; - init.parent_names = &pname; - init.num_parents = 1; - - pll->hw.init = &init; - pll->con_reg = con_reg; - pll->type = type; - - clk = clk_register(NULL, &pll->hw); - if (IS_ERR(clk)) { - pr_err("%s: failed to register pll clock %s\n", __func__, - name); - kfree(pll); - } - - if (clk_register_clkdev(clk, name, NULL)) - pr_err("%s: failed to register lookup for %s", __func__, name); - - return clk; -} - /* * PLL6552 Clock Type */ @@ -799,6 +754,11 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk, else init.ops = &samsung_pll36xx_clk_ops; break; + case pll_4600: + case pll_4650: + case pll_4650c: + init.ops = &samsung_pll46xx_clk_ops; + break; default: pr_warn("%s: Unknown pll type for pll clk %s\n", __func__, pll_clk->name); diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index aa8cc15..7de5e3e 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -19,7 +19,10 @@ enum samsung_pll_type { pll_2650, pll_4500, pll_4502, - pll_4508 + pll_4508, + pll_4600, + pll_4650, + pll_4650c, }; #define PLL_35XX_RATE(_rate, _m, _p, _s) \ @@ -59,15 +62,6 @@ struct samsung_pll_rate_table { unsigned int afc; }; -enum pll46xx_type { - pll_4600, - pll_4650, - pll_4650c, -}; - -extern struct clk * __init samsung_clk_register_pll46xx(const char *name, - const char *pname, const void __iomem *con_reg, - enum pll46xx_type type); extern struct clk *samsung_clk_register_pll6552(const char *name, const char *pname, void __iomem *base); extern struct clk *samsung_clk_register_pll6553(const char *name,