From patchwork Tue Aug 20 17:31:39 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 2847215 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2C1CABF546 for ; Tue, 20 Aug 2013 17:32:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D2C1720451 for ; Tue, 20 Aug 2013 17:32:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6640820547 for ; Tue, 20 Aug 2013 17:32:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751858Ab3HTRcP (ORCPT ); Tue, 20 Aug 2013 13:32:15 -0400 Received: from mailout3.w1.samsung.com ([210.118.77.13]:41640 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751822Ab3HTRcI (ORCPT ); Tue, 20 Aug 2013 13:32:08 -0400 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout3.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MRU0051UBD7UJE0@mailout3.w1.samsung.com>; Tue, 20 Aug 2013 18:32:07 +0100 (BST) X-AuditID: cbfec7f5-b7f5f6d00000105f-ba-5213a8163196 Received: from eusync3.samsung.com ( [203.254.199.213]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id 01.34.04191.618A3125; Tue, 20 Aug 2013 18:32:07 +0100 (BST) Received: from amdc1227.digital.local ([106.116.147.199]) by eusync3.samsung.com (Oracle Communications Messaging Server 7u4-23.01(7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0MRU00779BD55310@eusync3.samsung.com>; Tue, 20 Aug 2013 18:32:06 +0100 (BST) From: Tomasz Figa To: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, Kukjin Kim , Mike Turquette , Daniel Lezcano , Mark Rutland , Pawel Moll , Rob Herring , Stephen Warren , Thomas Abraham , Thomas Gleixner , Tushar Behera , Yadwinder Singh Brar , Doug Anderson , Kumar Gala , Tomasz Figa , Kyungmin Park Subject: [PATCH 12/16] clk: samsung: pll: Add support for rate configuration of PLL46xx Date: Tue, 20 Aug 2013 19:31:39 +0200 Message-id: <1377019903-14614-13-git-send-email-t.figa@samsung.com> X-Mailer: git-send-email 1.8.3.2 In-reply-to: <1377019903-14614-1-git-send-email-t.figa@samsung.com> References: <1377019903-14614-1-git-send-email-t.figa@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrCLMWRmVeSWpSXmKPExsVy+t/xq7riK4SDDBbMY7SY91nWYv6Rc6wW Z5cdZLPof7OQ1aJ3wVU2i7NNb9gtNj2+xmox4/w+Joul1y8yWTydcJHNYsL0tSwWh1ccYLJ4 dbCNxWL9jNcsFps3TWW2ODZjCaNF+9+9bBZzpr9jchDyWDNvDaPHgs9X2D1mN1xk8bjc18vk cefaHjaPd+fOsXtsXlLv0bdlFaPH501yHhvnhgZwRXHZpKTmZJalFunbJXBlTJ64gq3glmFF w8LrLA2MszW6GDk5JARMJN4+f8kKYYtJXLi3nq2LkYtDSGApo8TOC02sEE4fk8SztevAqtgE 1CQ+NzxiA7FFBDQkpnQ9ZgcpYhZYzCpx6+JLRpCEsECkxNsry8BsFgFViRU9p8CaeQWcJWb9 Os8OsU5BYtmXtcwgNidQfMOipWA1QgJOEp37FrFNYORdwMiwilE0tTS5oDgpPddIrzgxt7g0 L10vOT93EyMk5L/uYFx6zOoQowAHoxIPL0eJcJAQa2JZcWXuIUYJDmYlEd5tGUAh3pTEyqrU ovz4otKc1OJDjEwcnFINjMGpWzfLTvIWX9uSzJ4dOfu9lcMyJa25Qo2e7poibkdYio/IPjl9 Ly2uwdvzS0Vhm5vAMzNPM779M2z+1bB3f370ZK616Czu7OCoh9wK7avtrF4YaDxZ/Sh2Rd91 fZX3LR7P76l/CTCK29Xo80zMpuxkWu/N7KnseZ2fpJh1MhqSOYul7Q4psRRnJBpqMRcVJwIA xQP1rlcCAAA= Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch implements round_rate and set_rate callbacks of PLL46xx driver to allow reconfiguration of PLL at runtime. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park --- drivers/clk/samsung/clk-pll.c | 111 +++++++++++++++++++++++++++++++++++++++++- drivers/clk/samsung/clk-pll.h | 25 ++++++++++ 2 files changed, 135 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 8a008ca..c1f1c87 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -410,10 +410,13 @@ static const struct clk_ops samsung_pll45xx_clk_min_ops = { /* * PLL46xx Clock Type */ +#define PLL46XX_LOCK_FACTOR 3000 +#define PLL46XX_VSEL_MASK (1) #define PLL46XX_MDIV_MASK (0x1FF) #define PLL46XX_PDIV_MASK (0x3F) #define PLL46XX_SDIV_MASK (0x7) +#define PLL46XX_VSEL_SHIFT (27) #define PLL46XX_MDIV_SHIFT (16) #define PLL46XX_PDIV_SHIFT (8) #define PLL46XX_SDIV_SHIFT (0) @@ -421,6 +424,15 @@ static const struct clk_ops samsung_pll45xx_clk_min_ops = { #define PLL46XX_KDIV_MASK (0xFFFF) #define PLL4650C_KDIV_MASK (0xFFF) #define PLL46XX_KDIV_SHIFT (0) +#define PLL46XX_MFR_MASK (0x3F) +#define PLL46XX_MRR_MASK (0x1F) +#define PLL46XX_KDIV_SHIFT (0) +#define PLL46XX_MFR_SHIFT (16) +#define PLL46XX_MRR_SHIFT (24) + +#define PLL46XX_ENABLE BIT(31) +#define PLL46XX_LOCKED BIT(29) +#define PLL46XX_VSEL BIT(27) static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) @@ -445,8 +457,102 @@ static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw, return (unsigned long)fvco; } +static bool samsung_pll46xx_mpk_change(u32 pll_con0, u32 pll_con1, + const struct samsung_pll_rate_table *rate) +{ + u32 old_mdiv, old_pdiv, old_kdiv; + + old_mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK; + old_pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; + old_kdiv = (pll_con1 >> PLL46XX_KDIV_SHIFT) & PLL46XX_KDIV_MASK; + + return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv + || old_kdiv != rate->kdiv); +} + +static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + const struct samsung_pll_rate_table *rate; + u32 con0, con1, lock; + ktime_t start; + + /* Get required rate settings from table */ + rate = samsung_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, __clk_get_name(hw->clk)); + return -EINVAL; + } + + con0 = __raw_readl(pll->con_reg); + con1 = __raw_readl(pll->con_reg + 0x4); + + if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) { + /* If only s change, change just s value only*/ + con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); + con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT; + __raw_writel(con0, pll->con_reg); + + return 0; + } + + /* Set PLL lock time. */ + lock = rate->pdiv * PLL46XX_LOCK_FACTOR; + if (lock > 0xffff) + /* Maximum lock time bitfield is 16-bit. */ + lock = 0xffff; + + /* Set PLL PMS and VSEL values. */ + con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) | + (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) | + (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT) | + (PLL46XX_VSEL_MASK << PLL46XX_VSEL_SHIFT)); + con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) | + (rate->pdiv << PLL46XX_PDIV_SHIFT) | + (rate->sdiv << PLL46XX_SDIV_SHIFT) | + (rate->vsel << PLL46XX_VSEL_SHIFT); + + /* Set PLL AFC, MFR and MRR values. */ + con1 = __raw_readl(pll->con_reg + 0x4); + con1 &= ~((PLL46XX_KDIV_MASK << PLL46XX_KDIV_SHIFT) | + (PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT) | + (PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT)); + con1 |= (rate->kdiv << PLL46XX_KDIV_SHIFT) | + (rate->mfr << PLL46XX_MFR_SHIFT) | + (rate->mrr << PLL46XX_MRR_SHIFT); + + /* Write configuration to PLL */ + __raw_writel(lock, pll->lock_reg); + __raw_writel(con0, pll->con_reg); + __raw_writel(con1, pll->con_reg + 0x4); + + /* Wait for locking. */ + start = ktime_get(); + while (!(__raw_readl(pll->con_reg) & PLL46XX_LOCKED)) { + ktime_t delta = ktime_sub(ktime_get(), start); + + if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) { + pr_err("%s: could not lock PLL %s\n", + __func__, __clk_get_name(hw->clk)); + return -EFAULT; + } + + cpu_relax(); + } + + return 0; +} + static const struct clk_ops samsung_pll46xx_clk_ops = { .recalc_rate = samsung_pll46xx_recalc_rate, + .round_rate = samsung_pll_round_rate, + .set_rate = samsung_pll46xx_set_rate, +}; + +static const struct clk_ops samsung_pll46xx_clk_min_ops = { + .recalc_rate = samsung_pll46xx_recalc_rate, }; /* @@ -757,7 +863,10 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk, case pll_4600: case pll_4650: case pll_4650c: - init.ops = &samsung_pll46xx_clk_ops; + if (!pll->rate_table) + init.ops = &samsung_pll46xx_clk_min_ops; + else + init.ops = &samsung_pll46xx_clk_ops; break; default: pr_warn("%s: Unknown pll type for pll clk %s\n", diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 7de5e3e..53847e0 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -51,6 +51,28 @@ enum samsung_pll_type { .afc = (_afc), \ } +#define PLL_4600_RATE(_rate, _m, _p, _s, _k, _vsel) \ + { \ + .rate = (_rate), \ + .mdiv = (_m), \ + .pdiv = (_p), \ + .sdiv = (_s), \ + .kdiv = (_k), \ + .vsel = (_vsel), \ + } + +#define PLL_4650_RATE(_rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \ + { \ + .rate = (_rate), \ + .mdiv = (_m), \ + .pdiv = (_p), \ + .sdiv = (_s), \ + .kdiv = (_k), \ + .mfr = (_mfr), \ + .mrr = (_mrr), \ + .vsel = (_vsel), \ + } + /* NOTE: Rate table should be kept sorted in descending order. */ struct samsung_pll_rate_table { @@ -60,6 +82,9 @@ struct samsung_pll_rate_table { unsigned int sdiv; unsigned int kdiv; unsigned int afc; + unsigned int mfr; + unsigned int mrr; + unsigned int vsel; }; extern struct clk *samsung_clk_register_pll6552(const char *name,