From patchwork Tue Aug 20 17:31:41 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 2847217 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id AF051BF546 for ; Tue, 20 Aug 2013 17:32:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7CD7520451 for ; Tue, 20 Aug 2013 17:32:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 087A72054D for ; Tue, 20 Aug 2013 17:32:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751864Ab3HTRcR (ORCPT ); Tue, 20 Aug 2013 13:32:17 -0400 Received: from mailout4.w1.samsung.com ([210.118.77.14]:37444 "EHLO mailout4.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751380Ab3HTRcJ (ORCPT ); Tue, 20 Aug 2013 13:32:09 -0400 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout4.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MRU00H1SBCVOFD0@mailout4.w1.samsung.com>; Tue, 20 Aug 2013 18:32:08 +0100 (BST) X-AuditID: cbfec7f4-b7f5f6d000000ff6-5d-5213a818cf50 Received: from eusync3.samsung.com ( [203.254.199.213]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id 64.F7.04086.818A3125; Tue, 20 Aug 2013 18:32:08 +0100 (BST) Received: from amdc1227.digital.local ([106.116.147.199]) by eusync3.samsung.com (Oracle Communications Messaging Server 7u4-23.01(7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0MRU00779BD55310@eusync3.samsung.com>; Tue, 20 Aug 2013 18:32:08 +0100 (BST) From: Tomasz Figa To: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, Kukjin Kim , Mike Turquette , Daniel Lezcano , Mark Rutland , Pawel Moll , Rob Herring , Stephen Warren , Thomas Abraham , Thomas Gleixner , Tushar Behera , Yadwinder Singh Brar , Doug Anderson , Kumar Gala , Tomasz Figa , Kyungmin Park Subject: [PATCH 14/16] clk: samsung: exynos4: Register PLL rate tables for Exynos4210 Date: Tue, 20 Aug 2013 19:31:41 +0200 Message-id: <1377019903-14614-15-git-send-email-t.figa@samsung.com> X-Mailer: git-send-email 1.8.3.2 In-reply-to: <1377019903-14614-1-git-send-email-t.figa@samsung.com> References: <1377019903-14614-1-git-send-email-t.figa@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrELMWRmVeSWpSXmKPExsVy+t/xq7oSK4SDDC49lLeY91nWYv6Rc6wW Z5cdZLPof7OQ1aJ3wVU2i7NNb9gtNj2+xmox4/w+Joul1y8yWTydcJHNYsL0tSwWh1ccYLJ4 dbCNxWL9jNcsFps3TWW2ODZjCaNF+9+9bBZzpr9jchDyWDNvDaPHgs9X2D1mN1xk8bjc18vk cefaHjaPd+fOsXtsXlLv0bdlFaPH501yHhvnhgZwRXHZpKTmZJalFunbJXBlbPt+k7VggnjF gd1P2BsYm4S7GDk5JARMJN593MEKYYtJXLi3ng3EFhJYyijx8mwGhN3HJHHlUiCIzSagJvG5 4RFYjYiAhsSUrsfsXYxcHMwCi1klbl18yQiSEBYIl2j7MxtsKIuAqkT/jdVMIDavgLPE+lP/ 2SGWKUgs+7KWGcTmBIpvWLSUFWKZk0TnvkVsExh5FzAyrGIUTS1NLihOSs811CtOzC0uzUvX S87P3cQICfcvOxgXH7M6xCjAwajEw7uhUDhIiDWxrLgy9xCjBAezkgjvtgygEG9KYmVValF+ fFFpTmrxIUYmDk6pBkatrT/CV6Y/X39d+u/8789XPrV0vpj4kGHW9jnLOjULgp8ZKEnWrQqb ZTpPdfKF5i7L+IKzKyQMZu3QDC/aXLBkd2m92m/vg41ll15ZOIQdkjx++HdWQYL8j4z3E68Y zM7vDw79Nb9m9z1Zlx/S5WtZnKakmgdVfmcO//HQptlkv51j9cKH52crsRRnJBpqMRcVJwIA j+fRWFUCAAA= Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds rate tables for PLLs that can be reconfigured at runtime for Exynos4210 SoCs. Provided tables contain PLL coefficients for input clock of 24 MHz and so are registered only in this case. MPLL does not need runtime reconfiguration and so table for it is not provided. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park --- drivers/clk/samsung/clk-exynos4.c | 45 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 34474ce..e18cfae 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -992,6 +992,40 @@ static struct of_device_id ext_clk_match[] __initdata = { {}, }; +/* PLLs PMS values */ +static struct samsung_pll_rate_table exynos4210_apll_rates[] = { + PLL_45XX_RATE(1200000000, 150, 3, 1, 28), + PLL_45XX_RATE(1000000000, 250, 6, 1, 28), + PLL_45XX_RATE( 800000000, 200, 6, 1, 28), + PLL_45XX_RATE( 666857142, 389, 14, 1, 13), + PLL_45XX_RATE( 600000000, 100, 4, 1, 13), + PLL_45XX_RATE( 533000000, 533, 24, 1, 5), + PLL_45XX_RATE( 500000000, 250, 6, 2, 28), + PLL_45XX_RATE( 400000000, 200, 6, 2, 28), + PLL_45XX_RATE( 200000000, 200, 6, 3, 28), + { /* sentinel */ } +}; + +static struct samsung_pll_rate_table exynos4210_epll_rates[] = { + PLL_4600_RATE(192000000, 48, 3, 1, 0, 0), + PLL_4600_RATE(180633605, 45, 3, 1, 10381, 0), + PLL_4600_RATE(180000000, 45, 3, 1, 0, 0), + PLL_4600_RATE( 73727996, 73, 3, 3, 47710, 1), + PLL_4600_RATE( 67737602, 90, 4, 3, 20762, 1), + PLL_4600_RATE( 49151992, 49, 3, 3, 9961, 0), + PLL_4600_RATE( 45158401, 45, 3, 3, 10381, 0), + { /* sentinel */ } +}; + +static struct samsung_pll_rate_table exynos4210_vpll_rates[] = { + PLL_4650_RATE(360000000, 44, 3, 0, 1024, 0, 14, 0), + PLL_4650_RATE(324000000, 53, 2, 1, 1024, 1, 1, 1), + PLL_4650_RATE(259617187, 63, 3, 1, 1950, 0, 20, 1), + PLL_4650_RATE(110000000, 53, 3, 2, 2048, 0, 17, 0), + PLL_4650_RATE( 55360351, 53, 3, 3, 2417, 0, 17, 0), + { /* sentinel */ } +}; + static struct __initdata samsung_pll_clock exynos4210_plls[nr_plls] = { [apll] = PLL_A(pll_4508, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, APLL_CON0, "fout_apll", NULL), @@ -1042,6 +1076,17 @@ static void __init exynos4_clk_init(struct device_node *np, samsung_clk_register_mux(exynos4210_mux_early, ARRAY_SIZE(exynos4210_mux_early)); + if (_get_rate("fin_pll") == 24000000) { + exynos4210_plls[apll].rate_table = + exynos4210_apll_rates; + exynos4210_plls[epll].rate_table = + exynos4210_epll_rates; + } + + if (_get_rate("mout_vpllsrc") == 24000000) + exynos4210_plls[vpll].rate_table = + exynos4210_vpll_rates; + samsung_clk_register_pll(exynos4210_plls, ARRAY_SIZE(exynos4210_plls), reg_base); } else {