From patchwork Tue Aug 20 17:31:42 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 2847218 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A90DBBF546 for ; Tue, 20 Aug 2013 17:32:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8314720451 for ; Tue, 20 Aug 2013 17:32:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7CDAE20547 for ; Tue, 20 Aug 2013 17:32:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751866Ab3HTRcS (ORCPT ); Tue, 20 Aug 2013 13:32:18 -0400 Received: from mailout3.w1.samsung.com ([210.118.77.13]:41662 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751420Ab3HTRcL (ORCPT ); Tue, 20 Aug 2013 13:32:11 -0400 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout3.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MRU0051UBD7UJE0@mailout3.w1.samsung.com>; Tue, 20 Aug 2013 18:32:09 +0100 (BST) X-AuditID: cbfec7f5-b7f5f6d00000105f-ca-5213a819ad7d Received: from eusync3.samsung.com ( [203.254.199.213]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id A5.34.04191.918A3125; Tue, 20 Aug 2013 18:32:09 +0100 (BST) Received: from amdc1227.digital.local ([106.116.147.199]) by eusync3.samsung.com (Oracle Communications Messaging Server 7u4-23.01(7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0MRU00779BD55310@eusync3.samsung.com>; Tue, 20 Aug 2013 18:32:09 +0100 (BST) From: Tomasz Figa To: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, Kukjin Kim , Mike Turquette , Daniel Lezcano , Mark Rutland , Pawel Moll , Rob Herring , Stephen Warren , Thomas Abraham , Thomas Gleixner , Tushar Behera , Yadwinder Singh Brar , Doug Anderson , Kumar Gala , Tomasz Figa , Kyungmin Park Subject: [PATCH 15/16] clk: samsung: exynos4: Register PLL rate tables for Exynos4x12 Date: Tue, 20 Aug 2013 19:31:42 +0200 Message-id: <1377019903-14614-16-git-send-email-t.figa@samsung.com> X-Mailer: git-send-email 1.8.3.2 In-reply-to: <1377019903-14614-1-git-send-email-t.figa@samsung.com> References: <1377019903-14614-1-git-send-email-t.figa@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrILMWRmVeSWpSXmKPExsVy+t/xq7qSK4SDDBa95beY91nWYv6Rc6wW Z5cdZLPof7OQ1aJ3wVU2i7NNb9gtNj2+xmox4/w+Joul1y8yWTydcJHNYsL0tSwWh1ccYLJ4 dbCNxWL9jNcsFps3TWW2ODZjCaNF+9+9bBZzpr9jchDyWDNvDaPHgs9X2D1mN1xk8bjc18vk cefaHjaPd+fOsXtsXlLv0bdlFaPH501yHhvnhgZwRXHZpKTmZJalFunbJXBl/P11jKlgoUTF y+/iDYwtIl2MnBwSAiYSc5oPskPYYhIX7q1n62Lk4hASWMooMWVOKwuE08cksXBuOytIFZuA msTnhkdsILaIgIbElK7H7CBFzAKLWSVuXXzJ2MXIziEsEC6xkhukhEVAVWL2x/dgrbwCzhJL f55hglimILHsy1pmEJsTKL5h0VKwGiEBJ4nOfYvYJjDyLmBkWMUomlqaXFCclJ5rpFecmFtc mpeul5yfu4kREuxfdzAuPWZ1iFGAg1GJh5ejRDhIiDWxrLgy9xCjBAezkgjvtgygEG9KYmVV alF+fFFpTmrxIUYmDk6pBkbHeibFkj/MYgvj0n69WHdOwP+L3ccpWbUH9jUlJmWvmljRdWFT oGNyYPvOuM1HohcqTJwmr6RyzjbnxWmLXcclq0NuRjbd1UyvE15zdBavqKrh594vsmeOr5TL fd93bduJKuVVR27eqb4pdadDnJX5zKLile5HFPP7rSYeij2ede+wyY1rboeVWIozEg21mIuK EwE4VUoFVAIAAA== Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds rate tables for PLLs that can be reconfigured at runtime for Exynos4x12 SoCs. Provided tables contain PLL coefficients for input clock of 24 MHz and so are registered only in this case. MPLL does not need runtime reconfiguration and so table for it is not provided. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park --- drivers/clk/samsung/clk-exynos4.c | 49 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index e18cfae..8ab86f8 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -1026,6 +1026,46 @@ static struct samsung_pll_rate_table exynos4210_vpll_rates[] = { { /* sentinel */ } }; +static struct samsung_pll_rate_table exynos4x12_apll_rates[] = { + PLL_35XX_RATE(1500000000, 250, 4, 0), + PLL_35XX_RATE(1400000000, 175, 3, 0), + PLL_35XX_RATE(1300000000, 325, 6, 0), + PLL_35XX_RATE(1200000000, 200, 4, 0), + PLL_35XX_RATE(1100000000, 275, 6, 0), + PLL_35XX_RATE(1000000000, 125, 3, 0), + PLL_35XX_RATE( 900000000, 150, 4, 0), + PLL_35XX_RATE( 800000000, 100, 3, 0), + PLL_35XX_RATE( 700000000, 175, 3, 1), + PLL_35XX_RATE( 600000000, 200, 4, 1), + PLL_35XX_RATE( 500000000, 125, 3, 1), + PLL_35XX_RATE( 400000000, 100, 3, 1), + PLL_35XX_RATE( 300000000, 200, 4, 2), + PLL_35XX_RATE( 200000000, 100, 3, 2), + { /* sentinel */ } +}; + +static struct samsung_pll_rate_table exynos4x12_epll_rates[] = { + PLL_36XX_RATE(192000000, 48, 3, 1, 0), + PLL_36XX_RATE(180633605, 45, 3, 1, 10381), + PLL_36XX_RATE(180000000, 45, 3, 1, 0), + PLL_36XX_RATE( 73727996, 73, 3, 3, 47710), + PLL_36XX_RATE( 67737602, 90, 4, 3, 20762), + PLL_36XX_RATE( 49151992, 49, 3, 3, 9961), + PLL_36XX_RATE( 45158401, 45, 3, 3, 10381), + { /* sentinel */ } +}; + +static struct samsung_pll_rate_table exynos4x12_vpll_rates[] = { + PLL_36XX_RATE(533000000, 133, 3, 1, 16384), + PLL_36XX_RATE(440000000, 110, 3, 1, 0), + PLL_36XX_RATE(350000000, 175, 3, 2, 0), + PLL_36XX_RATE(266000000, 133, 3, 2, 0), + PLL_36XX_RATE(160000000, 160, 3, 3, 0), + PLL_36XX_RATE(106031250, 53, 3, 2, 1024), + PLL_36XX_RATE( 53015625, 53, 3, 3, 1024), + { /* sentinel */ } +}; + static struct __initdata samsung_pll_clock exynos4210_plls[nr_plls] = { [apll] = PLL_A(pll_4508, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, APLL_CON0, "fout_apll", NULL), @@ -1090,6 +1130,15 @@ static void __init exynos4_clk_init(struct device_node *np, samsung_clk_register_pll(exynos4210_plls, ARRAY_SIZE(exynos4210_plls), reg_base); } else { + if (_get_rate("fin_pll") == 24000000) { + exynos4x12_plls[apll].rate_table = + exynos4x12_apll_rates; + exynos4x12_plls[epll].rate_table = + exynos4x12_epll_rates; + exynos4x12_plls[vpll].rate_table = + exynos4x12_vpll_rates; + } + samsung_clk_register_pll(exynos4x12_plls, ARRAY_SIZE(exynos4x12_plls), reg_base); }