diff mbox

[V3] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC

Message ID 1377172278-15161-1-git-send-email-yuvaraj.cd@samsung.com
State New, archived
Headers show

Commit Message

Yuvaraj CD Aug. 22, 2013, 11:51 a.m. UTC
This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.

changes since V2:
	1.dropped num-slots property from node as its not required
	  if number of card slots available is 1.

	2.Move the below properties
		a.fifo-depth
		b.card-detect-delay
		c.samsung,dw-mshc-ciu-div
		d.samsung,dw-mshc-sdr-timing
		e.samsung,dw-mshc-ddr-timing
	from board dts to SOC dts,as these are not board specific properties.

	3.Updated the binding document exynos-dw-mshc.txt.

changes since V1:
	1.disable node by status = disabled in SOC file
	2.enable node by status = okay in board specific file

Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
---
 .../devicetree/bindings/mmc/exynos-dw-mshc.txt     |    4 ++
 arch/arm/boot/dts/exynos5420-smdk5420.dts          |   26 ++++++++++
 arch/arm/boot/dts/exynos5420.dtsi                  |   51 ++++++++++++++++++++
 3 files changed, 81 insertions(+)

Comments

Tomasz Figa Aug. 22, 2013, 10:57 p.m. UTC | #1
Hi Yuvaraj,

On Thursday 22 of August 2013 17:21:18 Yuvaraj Kumar C D wrote:
> This patch adds the device tree node entries for exynos5420 SOC.
> Exynos5420 has a different version of DWMMC controller,so a new
> compatible string is used to distinguish it from the prior SOC's.
> 
> changes since V2:
> 	1.dropped num-slots property from node as its not required
> 	  if number of card slots available is 1.
> 
> 	2.Move the below properties
> 		a.fifo-depth
> 		b.card-detect-delay
> 		c.samsung,dw-mshc-ciu-div
> 		d.samsung,dw-mshc-sdr-timing
> 		e.samsung,dw-mshc-ddr-timing
> 	from board dts to SOC dts,as these are not board specific 
properties.
> 
> 	3.Updated the binding document exynos-dw-mshc.txt.
> 
> changes since V1:
> 	1.disable node by status = disabled in SOC file
> 	2.enable node by status = okay in board specific file
> 
> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
> ---
>  .../devicetree/bindings/mmc/exynos-dw-mshc.txt     |    4 ++
>  arch/arm/boot/dts/exynos5420-smdk5420.dts          |   26 ++++++++++
>  arch/arm/boot/dts/exynos5420.dtsi                  |   51
> ++++++++++++++++++++ 3 files changed, 81 insertions(+)

Please resend this patch with devicetree mailing list and other recipients 
added, as listed in MAINTAINERS file for Documentation/devicetree/ and 
arch/*/boot/dts/ directories.

Best regards,
Tomasz

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Doug Anderson Aug. 22, 2013, 11:53 p.m. UTC | #2
Hi,

Thanks for adding my Thomasz,

On Thu, Aug 22, 2013 at 4:51 AM, Yuvaraj Kumar C D <yuvaraj.cd@gmail.com> wrote:
> This patch adds the device tree node entries for exynos5420 SOC.
> Exynos5420 has a different version of DWMMC controller,so a new
> compatible string is used to distinguish it from the prior SOC's.
>
> changes since V2:
>         1.dropped num-slots property from node as its not required
>           if number of card slots available is 1.

Just to mention: this is actually not board specific.  No exynos
products support more than one slot.  ...and in fact apparently NOBODY
supports more than one slot.  I have a plan to post up a patch
removing multislot support whenever I have a free moment.

Anyway, what you did is fine.


>         2.Move the below properties
>                 a.fifo-depth

Right, not board-specific.  This is SoC specific.  Interestingly
enough you appear to have it wrong.  I have it on good authority that
5420 has a FIFO depth of 0x40 not 0x80.  Apparently the FIFO is 0x40
deep and 64 wide whereas the old FIFO is 0x80 deep and 32 wide.


>                 b.card-detect-delay
>                 c.samsung,dw-mshc-ciu-div
>                 d.samsung,dw-mshc-sdr-timing
>                 e.samsung,dw-mshc-ddr-timing

These ARE board specific, actually.  ...and Tomasz has pointed out.


> +       dwmmc_2: dwmmc2@12220000 {
> +               compatible = "samsung,exynos5420-dw-mshc";
> +               interrupts = <0 77 0>;
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               reg = <0x12220000 0x2000>;
> +               clocks = <&clock 353>, <&clock 134>;
> +               clock-names = "biu", "ciu";
> +               fifo-depth = <0x80>;
> +               card-detect-delay = <200>;
> +               samsung,dw-mshc-ciu-div = <3>;
> +               samsung,dw-mshc-sdr-timing = <2 3>;
> +               samsung,dw-mshc-ddr-timing = <1 2>;

Note: I have information that says that these timings are not correct
and that nearly always the "drive" timing should be 0 and the sample
timing 4.  ...but we haven't landed that change ourselves yet, so
maybe keeping the timings you have is right.


-Doug
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Yuvaraj CD Aug. 23, 2013, 6:25 a.m. UTC | #3
On Fri, Aug 23, 2013 at 5:23 AM, Doug Anderson <dianders@google.com> wrote:
> Hi,
>
> Thanks for adding my Thomasz,
>
> On Thu, Aug 22, 2013 at 4:51 AM, Yuvaraj Kumar C D <yuvaraj.cd@gmail.com> wrote:
>> This patch adds the device tree node entries for exynos5420 SOC.
>> Exynos5420 has a different version of DWMMC controller,so a new
>> compatible string is used to distinguish it from the prior SOC's.
>>
>> changes since V2:
>>         1.dropped num-slots property from node as its not required
>>           if number of card slots available is 1.
>
> Just to mention: this is actually not board specific.  No exynos
> products support more than one slot.  ...and in fact apparently NOBODY
> supports more than one slot.  I have a plan to post up a patch
> removing multislot support whenever I have a free moment.
>
> Anyway, what you did is fine.
>
>
>>         2.Move the below properties
>>                 a.fifo-depth
>
> Right, not board-specific.  This is SoC specific.  Interestingly
> enough you appear to have it wrong.  I have it on good authority that
> 5420 has a FIFO depth of 0x40 not 0x80.  Apparently the FIFO is 0x40
> deep and 64 wide whereas the old FIFO is 0x80 deep and 32 wide.
Ok.I will change fifo-depth to 0x40.
>
>
>>                 b.card-detect-delay
>>                 c.samsung,dw-mshc-ciu-div
>>                 d.samsung,dw-mshc-sdr-timing
>>                 e.samsung,dw-mshc-ddr-timing
>
> These ARE board specific, actually.  ...and Tomasz has pointed out.
I am not sure, why these properties are not SOC specific?How these
properties value
will change in other variants(boards) of exynos5420?

>
>
>> +       dwmmc_2: dwmmc2@12220000 {
>> +               compatible = "samsung,exynos5420-dw-mshc";
>> +               interrupts = <0 77 0>;
>> +               #address-cells = <1>;
>> +               #size-cells = <0>;
>> +               reg = <0x12220000 0x2000>;
>> +               clocks = <&clock 353>, <&clock 134>;
>> +               clock-names = "biu", "ciu";
>> +               fifo-depth = <0x80>;
>> +               card-detect-delay = <200>;
>> +               samsung,dw-mshc-ciu-div = <3>;
>> +               samsung,dw-mshc-sdr-timing = <2 3>;
>> +               samsung,dw-mshc-ddr-timing = <1 2>;
>
> Note: I have information that says that these timings are not correct
> and that nearly always the "drive" timing should be 0 and the sample
> timing 4.  ...but we haven't landed that change ourselves yet, so
> maybe keeping the timings you have is right.
>
>
> -Doug
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Doug Anderson Aug. 24, 2013, 3:48 a.m. UTC | #4
Yuvaraj,

On Thu, Aug 22, 2013 at 11:25 PM, Yuvaraj Cd <yuvaraj.lkml@gmail.com> wrote:
>>>                 b.card-detect-delay
>>>                 c.samsung,dw-mshc-ciu-div
>>>                 d.samsung,dw-mshc-sdr-timing
>>>                 e.samsung,dw-mshc-ddr-timing

OK, so I don't know about card-detect-delay, but here's my belief
about the others.  Feel free to tell me I'm wrong, since I'm not an EE
by training and also the stuff below has been cobbled together from
lots of different docs.  I also haven't experimented enough to know
100% that it's correct.  I also know nothing about the actual
signaling protocols of SD/MMC...  Enough caveats?


sdr-timing / ddr-timing:

* First number (I think) allows you to drive data related lines at a
phase offset from the clock line.  So if you have crazy routing on
your board and the data lines are much longer than the clock lines you
might want to do this.  This is not common, so usually you want 0
here.  Note that some other docs I have disagree with this and claim
that this number has to do with hold time requirements.

* Second number allows you to sample signals from the card at a phase
offset from the clock line.  This number might depend on the card, but
hopefully not much.  It's supposed to depend more on the length of the
lines (AKA depends on the board), though it might also depend on
pullup values as well and somewhat on the card?  This number needs to
be tuned (like link training) when you operate a card at > 50MHz.

* For ciu-div:

With a ciu-div of 3 (really 3+1 = 4) you get phase offsets of 45 degrees.
With a ciu-div of 1 (really 1+1 = 2) you get phase offsets of 90 degrees.
WIth a ciu-div of 0 (really 0+1 = 1) you get no phase offsets (I would
have guessed 180, but manual says otherwise)

So ciu-div intimately affects the sdr-timing and ddr-timing.  Thus if
those are board-specific then so is ciu-div.

---

All of the above suggests to me the following untested things:

* If you happened to have a situation where you had a "ciu-div" of 3
and all of your sdr-timing/ddr-timing values were even, you could cut
the input clock in half, change "ciu-div" to 1, and cut all your
timings in half.  I'd imagine that would save you power (better to
slow clocks down higher in the clock tree?).  It would be sorta nice
if this was done automatically (assuming that you have full control of
input clock).

* I'm a little unclear exactly how the CLKDIV register interacts with
all of the above.  I guess I'd be under the assumption that the CLKDIV
applies to the main clock, the sample clock, and the drive clock.
...but maybe I'm confused.  I think you also get different results (in
terms of how many ns the drive and sample are delayed) depending on
whether the CLKDIV applies _after_ ciu-div or before.  My guess is
that it applies after.

---

Anyway, not sure that helps a whole lot, but that's a summary of what
I've come to understand.  I'm happy to be enlightened.  I'm still
trying to figure how how these numbers were picked for our hardware
and whether those numbers are actually right.

-Doug
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diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 6d1c098..25368e8 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -16,6 +16,8 @@  Required Properties:
 	  specific extensions.
 	- "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
 	  specific extensions.
+	- "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
+	  specific extensions.
 
 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
   unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
@@ -31,6 +33,8 @@  Required Properties:
   data rate mode operation. Refer notes below for the order of the cells and the
   valid values.
 
+* bypass-smu: Bypass Security Management Unit of eMMC channel 0 and channel 1.
+
   Notes for the sdr-timing and ddr-timing values:
 
     The order of the cells should be
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index bafba25..bc604d4 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -31,6 +31,32 @@ 
 		};
 	};
 
+	dwmmc0@12200000 {
+		status = "okay";
+		broken-cd;
+		bypass-smu;
+		supports-highspeed;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+
+		slot@0 {
+			reg = <0>;
+			bus-width = <8>;
+		};
+	};
+
+	dwmmc2@12220000 {
+		status = "okay";
+		supports-highspeed;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+
+		slot@0 {
+			reg = <0>;
+			bus-width = <4>;
+		};
+	};
+
 	dp-controller@145B0000 {
 		pinctrl-names = "default";
 		pinctrl-0 = <&dp_hpd>;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 5353e32..1f08d1b 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -22,6 +22,9 @@ 
 	compatible = "samsung,exynos5420";
 
 	aliases {
+		mshc0 = &dwmmc_0;
+		mshc1 = &dwmmc_1;
+		mshc2 = &dwmmc_2;
 		pinctrl0 = &pinctrl_0;
 		pinctrl1 = &pinctrl_1;
 		pinctrl2 = &pinctrl_2;
@@ -84,6 +87,54 @@ 
 		clock-names = "mfc";
 	};
 
+	dwmmc_0: dwmmc0@12200000 {
+		compatible = "samsung,exynos5420-dw-mshc";
+		interrupts = <0 75 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x12200000 0x2000>;
+		clocks = <&clock 351>, <&clock 132>;
+		clock-names = "biu", "ciu";
+		fifo-depth = <0x80>;
+		card-detect-delay = <200>;
+		samsung,dw-mshc-ciu-div = <3>;
+		samsung,dw-mshc-sdr-timing = <0 4>;
+		samsung,dw-mshc-ddr-timing = <0 2>;
+		status = "disabled";
+	};
+
+	dwmmc_1: dwmmc1@12210000 {
+		compatible = "samsung,exynos5420-dw-mshc";
+		interrupts = <0 76 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x12210000 0x2000>;
+		clocks = <&clock 352>, <&clock 133>;
+		clock-names = "biu", "ciu";
+		fifo-depth = <0x80>;
+		card-detect-delay = <200>;
+		samsung,dw-mshc-ciu-div = <3>;
+		samsung,dw-mshc-sdr-timing = <0 4>;
+		samsung,dw-mshc-ddr-timing = <0 2>;
+		status = "disabled";
+	};
+
+	dwmmc_2: dwmmc2@12220000 {
+		compatible = "samsung,exynos5420-dw-mshc";
+		interrupts = <0 77 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x12220000 0x2000>;
+		clocks = <&clock 353>, <&clock 134>;
+		clock-names = "biu", "ciu";
+		fifo-depth = <0x80>;
+		card-detect-delay = <200>;
+		samsung,dw-mshc-ciu-div = <3>;
+		samsung,dw-mshc-sdr-timing = <2 3>;
+		samsung,dw-mshc-ddr-timing = <1 2>;
+		status = "disabled";
+	};
+
 	mct@101C0000 {
 		compatible = "samsung,exynos4210-mct";
 		reg = <0x101C0000 0x800>;