From patchwork Mon Aug 26 17:08:59 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 2849704 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 97D5C9F2F4 for ; Mon, 26 Aug 2013 17:09:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5B58020255 for ; Mon, 26 Aug 2013 17:09:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E4A6B20362 for ; Mon, 26 Aug 2013 17:09:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756619Ab3HZRJw (ORCPT ); Mon, 26 Aug 2013 13:09:52 -0400 Received: from mailout3.w1.samsung.com ([210.118.77.13]:47978 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754896Ab3HZRJt (ORCPT ); Mon, 26 Aug 2013 13:09:49 -0400 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout3.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MS500NELEC81BD0@mailout3.w1.samsung.com>; Mon, 26 Aug 2013 18:09:47 +0100 (BST) X-AuditID: cbfec7f4-b7f0a6d000007b1b-d0-521b8bdb6e7f Received: from eusync1.samsung.com ( [203.254.199.211]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id 47.24.31515.BDB8B125; Mon, 26 Aug 2013 18:09:47 +0100 (BST) Received: from amdc1227.digital.local ([106.116.147.199]) by eusync1.samsung.com (Oracle Communications Messaging Server 7u4-23.01(7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0MS500C4SEC419A0@eusync1.samsung.com>; Mon, 26 Aug 2013 18:09:47 +0100 (BST) From: Tomasz Figa To: linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Kukjin Kim , Mike Turquette , Daniel Lezcano , Mark Rutland , Pawel Moll , Rob Herring , Stephen Warren , Thomas Abraham , Thomas Gleixner , Tushar Behera , Yadwinder Singh Brar , Doug Anderson , Kumar Gala , Tomasz Figa , Kyungmin Park Subject: [PATCH v2 04/16] clk: samsung: exynos4: Use separate aliases for cpufreq related clocks Date: Mon, 26 Aug 2013 19:08:59 +0200 Message-id: <1377536951-9307-5-git-send-email-t.figa@samsung.com> X-Mailer: git-send-email 1.8.3.2 In-reply-to: <1377536951-9307-1-git-send-email-t.figa@samsung.com> References: <1377536951-9307-1-git-send-email-t.figa@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrILMWRmVeSWpSXmKPExsVy+t/xy7q3u6WDDHb1q1vM+yxrMf/IOVaL s8sOsln0v1nIatG74CqbxdmmN+wWmx5fY7WYcX4fk8XS6xeZLJ5OuMhmMWH6WhaLwysOMFm8 OtjGYrF+xmsWi82bpjJbHJuxhNGi/e9eNos5098xOQh5rJm3htFjwecr7B6zGy6yeFzu62Xy uHNtD5vHu3Pn2D02L6n36NuyitHj8yY5j41zQwO4orhsUlJzMstSi/TtErgyLn5ZxlawW63i +849zA2MzxS6GDk5JARMJNqnXmGFsMUkLtxbz9bFyMUhJLCUUeLQqsNMEE4fk8TXvVvZQKrY BNQkPjc8ArNFBFQlPrctYAcpYhZYxipx/dJysISwQJLE8yWX2EFsFqCiRTceA63g4OAVcJRY 2pIMsU1BYtmXtcwgYU4BJ4l9/zNATCGgisndghMYeRcwMqxiFE0tTS4oTkrPNdQrTswtLs1L 10vOz93ECAn2LzsYFx+zOsQowMGoxMP7oEU6SIg1say4MvcQowQHs5IIL0cqUIg3JbGyKrUo P76oNCe1+BAjEwenVANjd8SKyQU2vXu/2DFNDYz6UGzuuyJDNFOvXn2G0emvV9OM8sVVV7MZ yu1z6HhWJnbm4EO1xScON59psM3bM780+4SfMGvo0aZyy4NqC/r3hJy5/KLr0krWOfn8BdfD vkyXY9Ez2uXeYJln0bytQnnxN8eztUZJ3vMdkyt9bB3zIm9qcrgxzVRiKc5INNRiLipOBABi U+PqVAIAAA== Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Exynos cpufreq driver is the only remaining piece of code that needs static clkdev aliases for operation, because it can not do device tree based clock lookups yet. This patch moves clock alias definitions for those clocks to separate arrays that can be used with samsung_clk_register_alias() helper. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park --- drivers/clk/samsung/clk-exynos4.c | 35 +++++++++++++++++++++++++++-------- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index f53658b..7de0769 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -392,9 +392,8 @@ static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1), MUX(none, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4), MUX(none, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4), - MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "mout_mpll"), - MUX_A(mout_core, "mout_core", mout_core_p4210, - SRC_CPU, 16, 1, "moutcore"), + MUX(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1), + MUX(mout_core, "mout_core", mout_core_p4210, SRC_CPU, 16, 1), MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1, "sclk_vpll"), MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), @@ -431,8 +430,8 @@ static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { /* list of mux clocks supported in exynos4x12 soc */ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { - MUX_A(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12, - SRC_CPU, 24, 1, "mout_mpll"), + MUX(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12, + SRC_CPU, 24, 1), MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1), MUX(none, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1), MUX(mout_mpll_user_t, "mout_mpll_user_t", mout_mpll_user_p4x12, @@ -456,8 +455,7 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { SRC_DMC, 12, 1, "sclk_mpll"), MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1, "sclk_vpll"), - MUX_A(mout_core, "mout_core", mout_core_p4x12, - SRC_CPU, 16, 1, "moutcore"), + MUX(mout_core, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1), MUX(mout_fimc0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4), MUX(mout_fimc1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4), MUX(mout_fimc2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4), @@ -545,7 +543,7 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = { DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), - DIV_A(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3, "armclk"), + DIV(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3), DIV_A(sclk_apll, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3, "sclk_apll"), DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4, @@ -930,6 +928,20 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { GATE(tmu_apbif, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, 0), }; +static struct samsung_clock_alias exynos4_aliases[] __initdata = { + ALIAS(mout_core, NULL, "moutcore"), + ALIAS(arm_clk, NULL, "armclk"), + ALIAS(sclk_apll, NULL, "mout_apll"), +}; + +static struct samsung_clock_alias exynos4210_aliases[] __initdata = { + ALIAS(sclk_mpll, NULL, "mout_mpll"), +}; + +static struct samsung_clock_alias exynos4x12_aliases[] __initdata = { + ALIAS(mout_mpll_user_c, NULL, "mout_mpll"), +}; + /* * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit * resides in chipid register space, outside of the clock controller memory @@ -1065,6 +1077,8 @@ static void __init exynos4_clk_init(struct device_node *np, ARRAY_SIZE(exynos4210_div_clks)); samsung_clk_register_gate(exynos4210_gate_clks, ARRAY_SIZE(exynos4210_gate_clks)); + samsung_clk_register_alias(exynos4210_aliases, + ARRAY_SIZE(exynos4210_aliases)); } else { samsung_clk_register_mux(exynos4x12_mux_clks, ARRAY_SIZE(exynos4x12_mux_clks)); @@ -1072,8 +1086,13 @@ static void __init exynos4_clk_init(struct device_node *np, ARRAY_SIZE(exynos4x12_div_clks)); samsung_clk_register_gate(exynos4x12_gate_clks, ARRAY_SIZE(exynos4x12_gate_clks)); + samsung_clk_register_alias(exynos4x12_aliases, + ARRAY_SIZE(exynos4x12_aliases)); } + samsung_clk_register_alias(exynos4_aliases, + ARRAY_SIZE(exynos4_aliases)); + pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n" "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n", exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",