diff mbox

[RFC,V3,4/4] mmc: dw_mmc: exynos: configure SMU in exynos5420.

Message ID 1377691731-7226-5-git-send-email-yuvaraj.cd@samsung.com
State New, archived
Headers show

Commit Message

Yuvaraj CD Aug. 28, 2013, 12:08 p.m. UTC
Exynos5420 Mobile Storage Host controller has Security Management Unit
(SMU) for channel 0 and channel 1 (mainly for eMMC).This patch configures
SMU for exynos5420.

This patch is on top of the below patch by Doug Anderson.
mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT

changes since V2:
	1.Droppped the bypass-smu quirk.
	2.Changed the subject line for this patch
	  add a quirk for SMU -> configure SMU in exynos5420

changes since V1:
	1.avoid code duplication by calling dw_mci_exynos_priv_init in
	  resume path.

Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/mmc/host/dw_mmc-exynos.c |   29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

Comments

Seungwon Jeon Aug. 29, 2013, 8:23 a.m. UTC | #1
On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
> Exynos5420 Mobile Storage Host controller has Security Management Unit
> (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch configures
> SMU for exynos5420.
> 
> This patch is on top of the below patch by Doug Anderson.
> mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
> 
> changes since V2:
> 	1.Droppped the bypass-smu quirk.
> 	2.Changed the subject line for this patch
> 	  add a quirk for SMU -> configure SMU in exynos5420
> 
> changes since V1:
> 	1.avoid code duplication by calling dw_mci_exynos_priv_init in
> 	  resume path.
> 
> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/mmc/host/dw_mmc-exynos.c |   29 +++++++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
> index 19c845b..db28f10 100644
> --- a/drivers/mmc/host/dw_mmc-exynos.c
> +++ b/drivers/mmc/host/dw_mmc-exynos.c
> @@ -35,6 +35,25 @@
>  #define EXYNOS4210_FIXED_CIU_CLK_DIV	2
>  #define EXYNOS4412_FIXED_CIU_CLK_DIV	4
> 
> +/* Block number in eMMC */
> +#define DWMCI_BLOCK_NUM			0xFFFFFFFF
> +
> +#define SDMMC_EMMCP_BASE		0x1000
> +#define SDMMC_MPSECURITY		(SDMMC_EMMCP_BASE + 0x0010)
> +#define SDMMC_MPSBEGIN0			(SDMMC_EMMCP_BASE + 0x0200)
> +#define SDMMC_MPSEND0			(SDMMC_EMMCP_BASE + 0x0204)
> +#define SDMMC_MPSCTRL0			(SDMMC_EMMCP_BASE + 0x020C)
> +
> +/* SMU control bits */
> +#define DWMCI_MPSCTRL_SECURE_READ_BIT		BIT(7)
> +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT		BIT(6)
> +#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT	BIT(5)
> +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT	BIT(4)
> +#define DWMCI_MPSCTRL_USE_FUSE_KEY		BIT(3)
> +#define DWMCI_MPSCTRL_ECB_MODE			BIT(2)
> +#define DWMCI_MPSCTRL_ENCRYPTION		BIT(1)
> +#define DWMCI_MPSCTRL_VALID			BIT(0)
> +
>  /* Variations in Exynos specific dw-mshc controller */
>  enum dw_mci_exynos_type {
>  	DW_MCI_TYPE_EXYNOS4210,
> @@ -74,6 +93,15 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
>  {
>  	struct dw_mci_exynos_priv_data *priv = host->priv;
> 
> +	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) {
> +		mci_writel(host, MPSBEGIN0, 0);
> +		mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
> +		mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
> +			DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
> +			DWMCI_MPSCTRL_VALID |
> +			DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
Yuvaraj,

Just one thing to check.
ch#0 and #1 of three hosts are only valid for SMU control.
Did you consider #2 host?
It seems not.

Thanks,
Seungwon Jeon

> +	}
> +
>  	return 0;
>  }
> 
> @@ -107,6 +135,7 @@ static int dw_mci_exynos_resume(struct device *dev)
>  {
>  	struct dw_mci *host = dev_get_drvdata(dev);
> 
> +	dw_mci_exynos_priv_init(host);
>  	return dw_mci_resume(host);
>  }
> 
> --
> 1.7.9.5
> 
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Alim Akhtar Aug. 29, 2013, 9:08 a.m. UTC | #2
Hi Seungwon,

On Thu, Aug 29, 2013 at 1:53 PM, Seungwon Jeon <tgih.jun@samsung.com> wrote:
> On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
>> Exynos5420 Mobile Storage Host controller has Security Management Unit
>> (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch configures
>> SMU for exynos5420.
>>
>> This patch is on top of the below patch by Doug Anderson.
>> mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
>>
>> changes since V2:
>>       1.Droppped the bypass-smu quirk.
>>       2.Changed the subject line for this patch
>>         add a quirk for SMU -> configure SMU in exynos5420
>>
>> changes since V1:
>>       1.avoid code duplication by calling dw_mci_exynos_priv_init in
>>         resume path.
>>
>> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>> ---
>>  drivers/mmc/host/dw_mmc-exynos.c |   29 +++++++++++++++++++++++++++++
>>  1 file changed, 29 insertions(+)
>>
>> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
>> index 19c845b..db28f10 100644
>> --- a/drivers/mmc/host/dw_mmc-exynos.c
>> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>> @@ -35,6 +35,25 @@
>>  #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
>>  #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
>>
>> +/* Block number in eMMC */
>> +#define DWMCI_BLOCK_NUM                      0xFFFFFFFF
>> +
>> +#define SDMMC_EMMCP_BASE             0x1000
>> +#define SDMMC_MPSECURITY             (SDMMC_EMMCP_BASE + 0x0010)
>> +#define SDMMC_MPSBEGIN0                      (SDMMC_EMMCP_BASE + 0x0200)
>> +#define SDMMC_MPSEND0                        (SDMMC_EMMCP_BASE + 0x0204)
>> +#define SDMMC_MPSCTRL0                       (SDMMC_EMMCP_BASE + 0x020C)
>> +
>> +/* SMU control bits */
>> +#define DWMCI_MPSCTRL_SECURE_READ_BIT                BIT(7)
>> +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT               BIT(6)
>> +#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT    BIT(5)
>> +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT   BIT(4)
>> +#define DWMCI_MPSCTRL_USE_FUSE_KEY           BIT(3)
>> +#define DWMCI_MPSCTRL_ECB_MODE                       BIT(2)
>> +#define DWMCI_MPSCTRL_ENCRYPTION             BIT(1)
>> +#define DWMCI_MPSCTRL_VALID                  BIT(0)
>> +
>>  /* Variations in Exynos specific dw-mshc controller */
>>  enum dw_mci_exynos_type {
>>       DW_MCI_TYPE_EXYNOS4210,
>> @@ -74,6 +93,15 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
>>  {
>>       struct dw_mci_exynos_priv_data *priv = host->priv;
>>
>> +     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) {
>> +             mci_writel(host, MPSBEGIN0, 0);
>> +             mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
>> +             mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
>> +                     DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
>> +                     DWMCI_MPSCTRL_VALID |
>> +                     DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
> Yuvaraj,
>
> Just one thing to check.
> ch#0 and #1 of three hosts are only valid for SMU control.
> Did you consider #2 host?
> It seems not.
>

Only host#0 and host#1 has SMU (On exynos5420).
Host #2 does not contain SMU.

> Thanks,
> Seungwon Jeon
>
>> +     }
>> +
>>       return 0;
>>  }
>>
>> @@ -107,6 +135,7 @@ static int dw_mci_exynos_resume(struct device *dev)
>>  {
>>       struct dw_mci *host = dev_get_drvdata(dev);
>>
>> +     dw_mci_exynos_priv_init(host);
>>       return dw_mci_resume(host);
>>  }
>>
>> --
>> 1.7.9.5
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
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Yuvaraj CD Aug. 29, 2013, 9:42 a.m. UTC | #3
On Thu, Aug 29, 2013 at 1:53 PM, Seungwon Jeon <tgih.jun@samsung.com> wrote:
> On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
>> Exynos5420 Mobile Storage Host controller has Security Management Unit
>> (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch configures
>> SMU for exynos5420.
>>
>> This patch is on top of the below patch by Doug Anderson.
>> mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
>>
>> changes since V2:
>>       1.Droppped the bypass-smu quirk.
>>       2.Changed the subject line for this patch
>>         add a quirk for SMU -> configure SMU in exynos5420
>>
>> changes since V1:
>>       1.avoid code duplication by calling dw_mci_exynos_priv_init in
>>         resume path.
>>
>> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>> ---
>>  drivers/mmc/host/dw_mmc-exynos.c |   29 +++++++++++++++++++++++++++++
>>  1 file changed, 29 insertions(+)
>>
>> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
>> index 19c845b..db28f10 100644
>> --- a/drivers/mmc/host/dw_mmc-exynos.c
>> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>> @@ -35,6 +35,25 @@
>>  #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
>>  #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
>>
>> +/* Block number in eMMC */
>> +#define DWMCI_BLOCK_NUM                      0xFFFFFFFF
>> +
>> +#define SDMMC_EMMCP_BASE             0x1000
>> +#define SDMMC_MPSECURITY             (SDMMC_EMMCP_BASE + 0x0010)
>> +#define SDMMC_MPSBEGIN0                      (SDMMC_EMMCP_BASE + 0x0200)
>> +#define SDMMC_MPSEND0                        (SDMMC_EMMCP_BASE + 0x0204)
>> +#define SDMMC_MPSCTRL0                       (SDMMC_EMMCP_BASE + 0x020C)
>> +
>> +/* SMU control bits */
>> +#define DWMCI_MPSCTRL_SECURE_READ_BIT                BIT(7)
>> +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT               BIT(6)
>> +#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT    BIT(5)
>> +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT   BIT(4)
>> +#define DWMCI_MPSCTRL_USE_FUSE_KEY           BIT(3)
>> +#define DWMCI_MPSCTRL_ECB_MODE                       BIT(2)
>> +#define DWMCI_MPSCTRL_ENCRYPTION             BIT(1)
>> +#define DWMCI_MPSCTRL_VALID                  BIT(0)
>> +
>>  /* Variations in Exynos specific dw-mshc controller */
>>  enum dw_mci_exynos_type {
>>       DW_MCI_TYPE_EXYNOS4210,
>> @@ -74,6 +93,15 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
>>  {
>>       struct dw_mci_exynos_priv_data *priv = host->priv;
>>
>> +     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) {
>> +             mci_writel(host, MPSBEGIN0, 0);
>> +             mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
>> +             mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
>> +                     DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
>> +                     DWMCI_MPSCTRL_VALID |
>> +                     DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
> Yuvaraj,
>
> Just one thing to check.
> ch#0 and #1 of three hosts are only valid for SMU control.
> Did you consider #2 host?
> It seems not.
Yes.AFAIK, host#2 doesn't have SMU.
>
> Thanks,
> Seungwon Jeon
>
>> +     }
>> +
>>       return 0;
>>  }
>>
>> @@ -107,6 +135,7 @@ static int dw_mci_exynos_resume(struct device *dev)
>>  {
>>       struct dw_mci *host = dev_get_drvdata(dev);
>>
>> +     dw_mci_exynos_priv_init(host);
>>       return dw_mci_resume(host);
>>  }
>>
>> --
>> 1.7.9.5
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
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Seungwon Jeon Aug. 29, 2013, 9:44 a.m. UTC | #4
On Thu, August 29, 2013, Alim Akhtar wrote:
> Hi Seungwon,
> 
> On Thu, Aug 29, 2013 at 1:53 PM, Seungwon Jeon <tgih.jun@samsung.com> wrote:
> > On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
> >> Exynos5420 Mobile Storage Host controller has Security Management Unit
> >> (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch configures
> >> SMU for exynos5420.
> >>
> >> This patch is on top of the below patch by Doug Anderson.
> >> mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
> >>
> >> changes since V2:
> >>       1.Droppped the bypass-smu quirk.
> >>       2.Changed the subject line for this patch
> >>         add a quirk for SMU -> configure SMU in exynos5420
> >>
> >> changes since V1:
> >>       1.avoid code duplication by calling dw_mci_exynos_priv_init in
> >>         resume path.
> >>
> >> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
> >> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> >> ---
> >>  drivers/mmc/host/dw_mmc-exynos.c |   29 +++++++++++++++++++++++++++++
> >>  1 file changed, 29 insertions(+)
> >>
> >> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
> >> index 19c845b..db28f10 100644
> >> --- a/drivers/mmc/host/dw_mmc-exynos.c
> >> +++ b/drivers/mmc/host/dw_mmc-exynos.c
> >> @@ -35,6 +35,25 @@
> >>  #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
> >>  #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
> >>
> >> +/* Block number in eMMC */
> >> +#define DWMCI_BLOCK_NUM                      0xFFFFFFFF
> >> +
> >> +#define SDMMC_EMMCP_BASE             0x1000
> >> +#define SDMMC_MPSECURITY             (SDMMC_EMMCP_BASE + 0x0010)
> >> +#define SDMMC_MPSBEGIN0                      (SDMMC_EMMCP_BASE + 0x0200)
> >> +#define SDMMC_MPSEND0                        (SDMMC_EMMCP_BASE + 0x0204)
> >> +#define SDMMC_MPSCTRL0                       (SDMMC_EMMCP_BASE + 0x020C)
> >> +
> >> +/* SMU control bits */
> >> +#define DWMCI_MPSCTRL_SECURE_READ_BIT                BIT(7)
> >> +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT               BIT(6)
> >> +#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT    BIT(5)
> >> +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT   BIT(4)
> >> +#define DWMCI_MPSCTRL_USE_FUSE_KEY           BIT(3)
> >> +#define DWMCI_MPSCTRL_ECB_MODE                       BIT(2)
> >> +#define DWMCI_MPSCTRL_ENCRYPTION             BIT(1)
> >> +#define DWMCI_MPSCTRL_VALID                  BIT(0)
> >> +
> >>  /* Variations in Exynos specific dw-mshc controller */
> >>  enum dw_mci_exynos_type {
> >>       DW_MCI_TYPE_EXYNOS4210,
> >> @@ -74,6 +93,15 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
> >>  {
> >>       struct dw_mci_exynos_priv_data *priv = host->priv;
> >>
> >> +     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) {
> >> +             mci_writel(host, MPSBEGIN0, 0);
> >> +             mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
> >> +             mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
> >> +                     DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
> >> +                     DWMCI_MPSCTRL_VALID |
> >> +                     DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
> > Yuvaraj,
> >
> > Just one thing to check.
> > ch#0 and #1 of three hosts are only valid for SMU control.
> > Did you consider #2 host?
> > It seems not.
> >
> 
> Only host#0 and host#1 has SMU (On exynos5420).
> Host #2 does not contain SMU.
Let me clear it.
I mean that current change allows for ch2 to access registers related to SMU,
even though ch2 doesn't actually has SMU. It's not valid IO area.

Thanks,
Seungwon Jeon

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Yuvaraj CD Aug. 29, 2013, 10:04 a.m. UTC | #5
On Thu, Aug 29, 2013 at 3:14 PM, Seungwon Jeon <tgih.jun@samsung.com> wrote:
> On Thu, August 29, 2013, Alim Akhtar wrote:
>> Hi Seungwon,
>>
>> On Thu, Aug 29, 2013 at 1:53 PM, Seungwon Jeon <tgih.jun@samsung.com> wrote:
>> > On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
>> >> Exynos5420 Mobile Storage Host controller has Security Management Unit
>> >> (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch configures
>> >> SMU for exynos5420.
>> >>
>> >> This patch is on top of the below patch by Doug Anderson.
>> >> mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
>> >>
>> >> changes since V2:
>> >>       1.Droppped the bypass-smu quirk.
>> >>       2.Changed the subject line for this patch
>> >>         add a quirk for SMU -> configure SMU in exynos5420
>> >>
>> >> changes since V1:
>> >>       1.avoid code duplication by calling dw_mci_exynos_priv_init in
>> >>         resume path.
>> >>
>> >> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
>> >> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>> >> ---
>> >>  drivers/mmc/host/dw_mmc-exynos.c |   29 +++++++++++++++++++++++++++++
>> >>  1 file changed, 29 insertions(+)
>> >>
>> >> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
>> >> index 19c845b..db28f10 100644
>> >> --- a/drivers/mmc/host/dw_mmc-exynos.c
>> >> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>> >> @@ -35,6 +35,25 @@
>> >>  #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
>> >>  #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
>> >>
>> >> +/* Block number in eMMC */
>> >> +#define DWMCI_BLOCK_NUM                      0xFFFFFFFF
>> >> +
>> >> +#define SDMMC_EMMCP_BASE             0x1000
>> >> +#define SDMMC_MPSECURITY             (SDMMC_EMMCP_BASE + 0x0010)
>> >> +#define SDMMC_MPSBEGIN0                      (SDMMC_EMMCP_BASE + 0x0200)
>> >> +#define SDMMC_MPSEND0                        (SDMMC_EMMCP_BASE + 0x0204)
>> >> +#define SDMMC_MPSCTRL0                       (SDMMC_EMMCP_BASE + 0x020C)
>> >> +
>> >> +/* SMU control bits */
>> >> +#define DWMCI_MPSCTRL_SECURE_READ_BIT                BIT(7)
>> >> +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT               BIT(6)
>> >> +#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT    BIT(5)
>> >> +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT   BIT(4)
>> >> +#define DWMCI_MPSCTRL_USE_FUSE_KEY           BIT(3)
>> >> +#define DWMCI_MPSCTRL_ECB_MODE                       BIT(2)
>> >> +#define DWMCI_MPSCTRL_ENCRYPTION             BIT(1)
>> >> +#define DWMCI_MPSCTRL_VALID                  BIT(0)
>> >> +
>> >>  /* Variations in Exynos specific dw-mshc controller */
>> >>  enum dw_mci_exynos_type {
>> >>       DW_MCI_TYPE_EXYNOS4210,
>> >> @@ -74,6 +93,15 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
>> >>  {
>> >>       struct dw_mci_exynos_priv_data *priv = host->priv;
>> >>
>> >> +     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) {
>> >> +             mci_writel(host, MPSBEGIN0, 0);
>> >> +             mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
>> >> +             mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
>> >> +                     DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
>> >> +                     DWMCI_MPSCTRL_VALID |
>> >> +                     DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
>> > Yuvaraj,
>> >
>> > Just one thing to check.
>> > ch#0 and #1 of three hosts are only valid for SMU control.
>> > Did you consider #2 host?
>> > It seems not.
>> >
>>
>> Only host#0 and host#1 has SMU (On exynos5420).
>> Host #2 does not contain SMU.
> Let me clear it.
> I mean that current change allows for ch2 to access registers related to SMU,
> even though ch2 doesn't actually has SMU. It's not valid IO area.
No,host#0 and host#1 are compatible with "samsung,exynos5420-dw-mshc"
but host#2 is compatible with the "samsung,exynos5250-dw-mshc".
Below is the DT patch posted in another thread.
[1] [PATCH V4] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg21985.html
I will resubmit the DT patch[1] with reg = <0x12220000 0x1000> for host#2.

>
> Thanks,
> Seungwon Jeon
>
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Yuvaraj CD Aug. 29, 2013, 10:10 a.m. UTC | #6
On Thu, Aug 29, 2013 at 3:34 PM, Yuvaraj Kumar <yuvaraj.cd@gmail.com> wrote:
> On Thu, Aug 29, 2013 at 3:14 PM, Seungwon Jeon <tgih.jun@samsung.com> wrote:
>> On Thu, August 29, 2013, Alim Akhtar wrote:
>>> Hi Seungwon,
>>>
>>> On Thu, Aug 29, 2013 at 1:53 PM, Seungwon Jeon <tgih.jun@samsung.com> wrote:
>>> > On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
>>> >> Exynos5420 Mobile Storage Host controller has Security Management Unit
>>> >> (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch configures
>>> >> SMU for exynos5420.
>>> >>
>>> >> This patch is on top of the below patch by Doug Anderson.
>>> >> mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
>>> >>
>>> >> changes since V2:
>>> >>       1.Droppped the bypass-smu quirk.
>>> >>       2.Changed the subject line for this patch
>>> >>         add a quirk for SMU -> configure SMU in exynos5420
>>> >>
>>> >> changes since V1:
>>> >>       1.avoid code duplication by calling dw_mci_exynos_priv_init in
>>> >>         resume path.
>>> >>
>>> >> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
>>> >> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>>> >> ---
>>> >>  drivers/mmc/host/dw_mmc-exynos.c |   29 +++++++++++++++++++++++++++++
>>> >>  1 file changed, 29 insertions(+)
>>> >>
>>> >> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
>>> >> index 19c845b..db28f10 100644
>>> >> --- a/drivers/mmc/host/dw_mmc-exynos.c
>>> >> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>>> >> @@ -35,6 +35,25 @@
>>> >>  #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
>>> >>  #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
>>> >>
>>> >> +/* Block number in eMMC */
>>> >> +#define DWMCI_BLOCK_NUM                      0xFFFFFFFF
>>> >> +
>>> >> +#define SDMMC_EMMCP_BASE             0x1000
>>> >> +#define SDMMC_MPSECURITY             (SDMMC_EMMCP_BASE + 0x0010)
>>> >> +#define SDMMC_MPSBEGIN0                      (SDMMC_EMMCP_BASE + 0x0200)
>>> >> +#define SDMMC_MPSEND0                        (SDMMC_EMMCP_BASE + 0x0204)
>>> >> +#define SDMMC_MPSCTRL0                       (SDMMC_EMMCP_BASE + 0x020C)
>>> >> +
>>> >> +/* SMU control bits */
>>> >> +#define DWMCI_MPSCTRL_SECURE_READ_BIT                BIT(7)
>>> >> +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT               BIT(6)
>>> >> +#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT    BIT(5)
>>> >> +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT   BIT(4)
>>> >> +#define DWMCI_MPSCTRL_USE_FUSE_KEY           BIT(3)
>>> >> +#define DWMCI_MPSCTRL_ECB_MODE                       BIT(2)
>>> >> +#define DWMCI_MPSCTRL_ENCRYPTION             BIT(1)
>>> >> +#define DWMCI_MPSCTRL_VALID                  BIT(0)
>>> >> +
>>> >>  /* Variations in Exynos specific dw-mshc controller */
>>> >>  enum dw_mci_exynos_type {
>>> >>       DW_MCI_TYPE_EXYNOS4210,
>>> >> @@ -74,6 +93,15 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
>>> >>  {
>>> >>       struct dw_mci_exynos_priv_data *priv = host->priv;
>>> >>
>>> >> +     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) {
>>> >> +             mci_writel(host, MPSBEGIN0, 0);
>>> >> +             mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
>>> >> +             mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
>>> >> +                     DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
>>> >> +                     DWMCI_MPSCTRL_VALID |
>>> >> +                     DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
>>> > Yuvaraj,
>>> >
>>> > Just one thing to check.
>>> > ch#0 and #1 of three hosts are only valid for SMU control.
>>> > Did you consider #2 host?
>>> > It seems not.
>>> >
>>>
>>> Only host#0 and host#1 has SMU (On exynos5420).
>>> Host #2 does not contain SMU.
>> Let me clear it.
>> I mean that current change allows for ch2 to access registers related to SMU,
>> even though ch2 doesn't actually has SMU. It's not valid IO area.
> No,host#0 and host#1 are compatible with "samsung,exynos5420-dw-mshc"
> but host#2 is compatible with the "samsung,exynos5250-dw-mshc".
 Below is the DT patch posted in another thread.(Sorry,earlier link
was bit older).
[PATCH V5] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg22074.html
I will resubmit the DT patch[1] with reg = <0x12220000 0x1000> for host#2.
>
>>
>> Thanks,
>> Seungwon Jeon
>>
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Seungwon Jeon Aug. 29, 2013, 10:36 a.m. UTC | #7
Yuvaraj Kumar wrote:
> On Thu, Aug 29, 2013 at 3:14 PM, Seungwon Jeon <tgih.jun@samsung.com> wrote:
> > On Thu, August 29, 2013, Alim Akhtar wrote:
> >> Hi Seungwon,
> >>
> >> On Thu, Aug 29, 2013 at 1:53 PM, Seungwon Jeon <tgih.jun@samsung.com> wrote:
> >> > On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
> >> >> Exynos5420 Mobile Storage Host controller has Security Management Unit
> >> >> (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch configures
> >> >> SMU for exynos5420.
> >> >>
> >> >> This patch is on top of the below patch by Doug Anderson.
> >> >> mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
> >> >>
> >> >> changes since V2:
> >> >>       1.Droppped the bypass-smu quirk.
> >> >>       2.Changed the subject line for this patch
> >> >>         add a quirk for SMU -> configure SMU in exynos5420
> >> >>
> >> >> changes since V1:
> >> >>       1.avoid code duplication by calling dw_mci_exynos_priv_init in
> >> >>         resume path.
> >> >>
> >> >> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
> >> >> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> >> >> ---
> >> >>  drivers/mmc/host/dw_mmc-exynos.c |   29 +++++++++++++++++++++++++++++
> >> >>  1 file changed, 29 insertions(+)
> >> >>
> >> >> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
> >> >> index 19c845b..db28f10 100644
> >> >> --- a/drivers/mmc/host/dw_mmc-exynos.c
> >> >> +++ b/drivers/mmc/host/dw_mmc-exynos.c
> >> >> @@ -35,6 +35,25 @@
> >> >>  #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
> >> >>  #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
> >> >>
> >> >> +/* Block number in eMMC */
> >> >> +#define DWMCI_BLOCK_NUM                      0xFFFFFFFF
> >> >> +
> >> >> +#define SDMMC_EMMCP_BASE             0x1000
> >> >> +#define SDMMC_MPSECURITY             (SDMMC_EMMCP_BASE + 0x0010)
> >> >> +#define SDMMC_MPSBEGIN0                      (SDMMC_EMMCP_BASE + 0x0200)
> >> >> +#define SDMMC_MPSEND0                        (SDMMC_EMMCP_BASE + 0x0204)
> >> >> +#define SDMMC_MPSCTRL0                       (SDMMC_EMMCP_BASE + 0x020C)
> >> >> +
> >> >> +/* SMU control bits */
> >> >> +#define DWMCI_MPSCTRL_SECURE_READ_BIT                BIT(7)
> >> >> +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT               BIT(6)
> >> >> +#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT    BIT(5)
> >> >> +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT   BIT(4)
> >> >> +#define DWMCI_MPSCTRL_USE_FUSE_KEY           BIT(3)
> >> >> +#define DWMCI_MPSCTRL_ECB_MODE                       BIT(2)
> >> >> +#define DWMCI_MPSCTRL_ENCRYPTION             BIT(1)
> >> >> +#define DWMCI_MPSCTRL_VALID                  BIT(0)
> >> >> +
> >> >>  /* Variations in Exynos specific dw-mshc controller */
> >> >>  enum dw_mci_exynos_type {
> >> >>       DW_MCI_TYPE_EXYNOS4210,
> >> >> @@ -74,6 +93,15 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
> >> >>  {
> >> >>       struct dw_mci_exynos_priv_data *priv = host->priv;
> >> >>
> >> >> +     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) {
> >> >> +             mci_writel(host, MPSBEGIN0, 0);
> >> >> +             mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
> >> >> +             mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
> >> >> +                     DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
> >> >> +                     DWMCI_MPSCTRL_VALID |
> >> >> +                     DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
> >> > Yuvaraj,
> >> >
> >> > Just one thing to check.
> >> > ch#0 and #1 of three hosts are only valid for SMU control.
> >> > Did you consider #2 host?
> >> > It seems not.
> >> >
> >>
> >> Only host#0 and host#1 has SMU (On exynos5420).
> >> Host #2 does not contain SMU.
> > Let me clear it.
> > I mean that current change allows for ch2 to access registers related to SMU,
> > even though ch2 doesn't actually has SMU. It's not valid IO area.
> No,host#0 and host#1 are compatible with "samsung,exynos5420-dw-mshc"
> but host#2 is compatible with the "samsung,exynos5250-dw-mshc".
> Below is the DT patch posted in another thread.
> [1] [PATCH V4] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
> http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg21985.html
> I will resubmit the DT patch[1] with reg = <0x12220000 0x1000> for host#2.

Hmm. If we notice exynos5420's other newly added registers apart from SMU, 
it is difficult to say exynos5420 is compatible with exynos5250 fully for #2.
But because there is no use case for new registers, it could be acceptable.
Ok, we should be careful to configure DT file though.

Thanks,
Seungwon Jeon

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Tomasz Figa Aug. 29, 2013, 11:46 a.m. UTC | #8
Hi Seungwon,

On Thursday 29 of August 2013 19:36:28 Seungwon Jeon wrote:
> Yuvaraj Kumar wrote:
> > On Thu, Aug 29, 2013 at 3:14 PM, Seungwon Jeon <tgih.jun@samsung.com> 
wrote:
> > > On Thu, August 29, 2013, Alim Akhtar wrote:
> > >> Hi Seungwon,
> > >> 
> > >> On Thu, Aug 29, 2013 at 1:53 PM, Seungwon Jeon 
<tgih.jun@samsung.com> wrote:
> > >> > On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
> > >> >> Exynos5420 Mobile Storage Host controller has Security Management
> > >> >> Unit
> > >> >> (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch
> > >> >> configures SMU for exynos5420.
> > >> >> 
> > >> >> This patch is on top of the below patch by Doug Anderson.
> > >> >> mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
> > >> >> 
> > >> >> changes since V2:
> > >> >>       1.Droppped the bypass-smu quirk.
> > >> >>       2.Changed the subject line for this patch
> > >> >>       
> > >> >>         add a quirk for SMU -> configure SMU in exynos5420
> > >> >> 
> > >> >> changes since V1:
> > >> >>       1.avoid code duplication by calling dw_mci_exynos_priv_init
> > >> >>       in
> > >> >>       
> > >> >>         resume path.
> > >> >> 
> > >> >> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
> > >> >> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> > >> >> ---
> > >> >> 
> > >> >>  drivers/mmc/host/dw_mmc-exynos.c |   29
> > >> >>  +++++++++++++++++++++++++++++
> > >> >>  1 file changed, 29 insertions(+)
> > >> >> 
> > >> >> diff --git a/drivers/mmc/host/dw_mmc-exynos.c
> > >> >> b/drivers/mmc/host/dw_mmc-exynos.c index 19c845b..db28f10 100644
> > >> >> --- a/drivers/mmc/host/dw_mmc-exynos.c
> > >> >> +++ b/drivers/mmc/host/dw_mmc-exynos.c
> > >> >> @@ -35,6 +35,25 @@
> > >> >> 
> > >> >>  #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
> > >> >>  #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
> > >> >> 
> > >> >> +/* Block number in eMMC */
> > >> >> +#define DWMCI_BLOCK_NUM                      0xFFFFFFFF
> > >> >> +
> > >> >> +#define SDMMC_EMMCP_BASE             0x1000
> > >> >> +#define SDMMC_MPSECURITY             (SDMMC_EMMCP_BASE + 0x0010)
> > >> >> +#define SDMMC_MPSBEGIN0                      (SDMMC_EMMCP_BASE +
> > >> >> 0x0200) +#define SDMMC_MPSEND0                       
> > >> >> (SDMMC_EMMCP_BASE + 0x0204) +#define SDMMC_MPSCTRL0             
> > >> >>          (SDMMC_EMMCP_BASE + 0x020C) +
> > >> >> +/* SMU control bits */
> > >> >> +#define DWMCI_MPSCTRL_SECURE_READ_BIT                BIT(7)
> > >> >> +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT               BIT(6)
> > >> >> +#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT    BIT(5)
> > >> >> +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT   BIT(4)
> > >> >> +#define DWMCI_MPSCTRL_USE_FUSE_KEY           BIT(3)
> > >> >> +#define DWMCI_MPSCTRL_ECB_MODE                       BIT(2)
> > >> >> +#define DWMCI_MPSCTRL_ENCRYPTION             BIT(1)
> > >> >> +#define DWMCI_MPSCTRL_VALID                  BIT(0)
> > >> >> +
> > >> >> 
> > >> >>  /* Variations in Exynos specific dw-mshc controller */
> > >> >>  enum dw_mci_exynos_type {
> > >> >>  
> > >> >>       DW_MCI_TYPE_EXYNOS4210,
> > >> >> 
> > >> >> @@ -74,6 +93,15 @@ static int dw_mci_exynos_priv_init(struct
> > >> >> dw_mci *host)> >> >> 
> > >> >>  {
> > >> >>  
> > >> >>       struct dw_mci_exynos_priv_data *priv = host->priv;
> > >> >> 
> > >> >> +     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) {
> > >> >> +             mci_writel(host, MPSBEGIN0, 0);
> > >> >> +             mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
> > >> >> +             mci_writel(host, MPSCTRL0,
> > >> >> DWMCI_MPSCTRL_SECURE_WRITE_BIT | +                    
> > >> >> DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
> > >> >> +                     DWMCI_MPSCTRL_VALID |
> > >> >> +                     DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
> > >> > 
> > >> > Yuvaraj,
> > >> > 
> > >> > Just one thing to check.
> > >> > ch#0 and #1 of three hosts are only valid for SMU control.
> > >> > Did you consider #2 host?
> > >> > It seems not.
> > >> 
> > >> Only host#0 and host#1 has SMU (On exynos5420).
> > >> Host #2 does not contain SMU.
> > > 
> > > Let me clear it.
> > > I mean that current change allows for ch2 to access registers related
> > > to SMU, even though ch2 doesn't actually has SMU. It's not valid IO
> > > area.> 
> > No,host#0 and host#1 are compatible with "samsung,exynos5420-dw-mshc"
> > but host#2 is compatible with the "samsung,exynos5250-dw-mshc".
> > Below is the DT patch posted in another thread.
> > [1] [PATCH V4] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
> > http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg21985.
> > html I will resubmit the DT patch[1] with reg = <0x12220000 0x1000> for
> > host#2.
> Hmm. If we notice exynos5420's other newly added registers apart from
> SMU, it is difficult to say exynos5420 is compatible with exynos5250
> fully for #2. But because there is no use case for new registers, it
> could be acceptable. Ok, we should be careful to configure DT file
> though.

Could you elaborate a bit more on the differences in DW MMC IP between 
Exynos5250 and Exynos5420? If the differences are significant, then it 
might be necessary to use different compatible value, as it should not 
depend on any use case (or lack of).

If the DW MMC version used in Exynos 5420 provides the whole set of 
functionality of the version used in Exynos 5250 and some extra extensions, 
then it can be called "compatible with Exynos 5250", but if you ever need 
to support those extra extensions, you will have to add a separate 
compatible string for it.

With regard to SMU that is present only on selected instances, you can as 
well create two compatible values for the DW MMC IP on Exynos 5420, e.g. 
"samsung,exynos5420-dw-mshc" and "samsung,exynos5420-dw-mshc-smu".

[Adding devicetree ML and DT maintainers on CC, as this is something they 
should be able to comment on.]

Best regards,
Tomasz

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Seungwon Jeon Aug. 30, 2013, 3:44 a.m. UTC | #9
On Thu, August 29, 2013, Tomasz Figa wrote:
> Hi Seungwon,
> 
> On Thursday 29 of August 2013 19:36:28 Seungwon Jeon wrote:
> > Yuvaraj Kumar wrote:
> > > On Thu, Aug 29, 2013 at 3:14 PM, Seungwon Jeon <tgih.jun@samsung.com>
> wrote:
> > > > On Thu, August 29, 2013, Alim Akhtar wrote:
> > > >> Hi Seungwon,
> > > >>
> > > >> On Thu, Aug 29, 2013 at 1:53 PM, Seungwon Jeon
> <tgih.jun@samsung.com> wrote:
> > > >> > On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
> > > >> >> Exynos5420 Mobile Storage Host controller has Security Management
> > > >> >> Unit
> > > >> >> (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch
> > > >> >> configures SMU for exynos5420.
> > > >> >>
> > > >> >> This patch is on top of the below patch by Doug Anderson.
> > > >> >> mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
> > > >> >>
> > > >> >> changes since V2:
> > > >> >>       1.Droppped the bypass-smu quirk.
> > > >> >>       2.Changed the subject line for this patch
> > > >> >>
> > > >> >>         add a quirk for SMU -> configure SMU in exynos5420
> > > >> >>
> > > >> >> changes since V1:
> > > >> >>       1.avoid code duplication by calling dw_mci_exynos_priv_init
> > > >> >>       in
> > > >> >>
> > > >> >>         resume path.
> > > >> >>
> > > >> >> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
> > > >> >> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> > > >> >> ---
> > > >> >>
> > > >> >>  drivers/mmc/host/dw_mmc-exynos.c |   29
> > > >> >>  +++++++++++++++++++++++++++++
> > > >> >>  1 file changed, 29 insertions(+)
> > > >> >>
> > > >> >> diff --git a/drivers/mmc/host/dw_mmc-exynos.c
> > > >> >> b/drivers/mmc/host/dw_mmc-exynos.c index 19c845b..db28f10 100644
> > > >> >> --- a/drivers/mmc/host/dw_mmc-exynos.c
> > > >> >> +++ b/drivers/mmc/host/dw_mmc-exynos.c
> > > >> >> @@ -35,6 +35,25 @@
> > > >> >>
> > > >> >>  #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
> > > >> >>  #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
> > > >> >>
> > > >> >> +/* Block number in eMMC */
> > > >> >> +#define DWMCI_BLOCK_NUM                      0xFFFFFFFF
> > > >> >> +
> > > >> >> +#define SDMMC_EMMCP_BASE             0x1000
> > > >> >> +#define SDMMC_MPSECURITY             (SDMMC_EMMCP_BASE + 0x0010)
> > > >> >> +#define SDMMC_MPSBEGIN0                      (SDMMC_EMMCP_BASE +
> > > >> >> 0x0200) +#define SDMMC_MPSEND0
> > > >> >> (SDMMC_EMMCP_BASE + 0x0204) +#define SDMMC_MPSCTRL0
> > > >> >>          (SDMMC_EMMCP_BASE + 0x020C) +
> > > >> >> +/* SMU control bits */
> > > >> >> +#define DWMCI_MPSCTRL_SECURE_READ_BIT                BIT(7)
> > > >> >> +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT               BIT(6)
> > > >> >> +#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT    BIT(5)
> > > >> >> +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT   BIT(4)
> > > >> >> +#define DWMCI_MPSCTRL_USE_FUSE_KEY           BIT(3)
> > > >> >> +#define DWMCI_MPSCTRL_ECB_MODE                       BIT(2)
> > > >> >> +#define DWMCI_MPSCTRL_ENCRYPTION             BIT(1)
> > > >> >> +#define DWMCI_MPSCTRL_VALID                  BIT(0)
> > > >> >> +
> > > >> >>
> > > >> >>  /* Variations in Exynos specific dw-mshc controller */
> > > >> >>  enum dw_mci_exynos_type {
> > > >> >>
> > > >> >>       DW_MCI_TYPE_EXYNOS4210,
> > > >> >>
> > > >> >> @@ -74,6 +93,15 @@ static int dw_mci_exynos_priv_init(struct
> > > >> >> dw_mci *host)> >> >>
> > > >> >>  {
> > > >> >>
> > > >> >>       struct dw_mci_exynos_priv_data *priv = host->priv;
> > > >> >>
> > > >> >> +     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) {
> > > >> >> +             mci_writel(host, MPSBEGIN0, 0);
> > > >> >> +             mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
> > > >> >> +             mci_writel(host, MPSCTRL0,
> > > >> >> DWMCI_MPSCTRL_SECURE_WRITE_BIT | +
> > > >> >> DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
> > > >> >> +                     DWMCI_MPSCTRL_VALID |
> > > >> >> +                     DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
> > > >> >
> > > >> > Yuvaraj,
> > > >> >
> > > >> > Just one thing to check.
> > > >> > ch#0 and #1 of three hosts are only valid for SMU control.
> > > >> > Did you consider #2 host?
> > > >> > It seems not.
> > > >>
> > > >> Only host#0 and host#1 has SMU (On exynos5420).
> > > >> Host #2 does not contain SMU.
> > > >
> > > > Let me clear it.
> > > > I mean that current change allows for ch2 to access registers related
> > > > to SMU, even though ch2 doesn't actually has SMU. It's not valid IO
> > > > area.>
> > > No,host#0 and host#1 are compatible with "samsung,exynos5420-dw-mshc"
> > > but host#2 is compatible with the "samsung,exynos5250-dw-mshc".
> > > Below is the DT patch posted in another thread.
> > > [1] [PATCH V4] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
> > > http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg21985.
> > > html I will resubmit the DT patch[1] with reg = <0x12220000 0x1000> for
> > > host#2.
> > Hmm. If we notice exynos5420's other newly added registers apart from
> > SMU, it is difficult to say exynos5420 is compatible with exynos5250
> > fully for #2. But because there is no use case for new registers, it
> > could be acceptable. Ok, we should be careful to configure DT file
> > though.
> 
> Could you elaborate a bit more on the differences in DW MMC IP between
> Exynos5250 and Exynos5420? If the differences are significant, then it
> might be necessary to use different compatible value, as it should not
> depend on any use case (or lack of).
Actually the reason is  that extended register of ch2 doesn't work rather than none of use case.
Ch2 is targeted for removable card type.

> 
> If the DW MMC version used in Exynos 5420 provides the whole set of
> functionality of the version used in Exynos 5250 and some extra extensions,
> then it can be called "compatible with Exynos 5250", but if you ever need
> to support those extra extensions, you will have to add a separate
> compatible string for it.
> 
> With regard to SMU that is present only on selected instances, you can as
> well create two compatible values for the DW MMC IP on Exynos 5420, e.g.
> "samsung,exynos5420-dw-mshc" and "samsung,exynos5420-dw-mshc-smu".
I think your suggestion is a nice thing. It makes sense.
And I missed one thing.
Apart from added register, Exynos5420 ch2 is designed for I/O of 1.2V voltage unlike Exynos5250.
So it is worthy to be distinguished.

Yuvaraj,
Could you apply Tomasz's suggestion ("samsung,exynos5420-dw-mshc" and "samsung,exynos5420-dw-mshc-smu") and resend it?

Thanks,
Seungwon Jeon

> 
> [Adding devicetree ML and DT maintainers on CC, as this is something they
> should be able to comment on.]
> 
> Best regards,
> Tomasz
> 
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diff mbox

Patch

diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 19c845b..db28f10 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -35,6 +35,25 @@ 
 #define EXYNOS4210_FIXED_CIU_CLK_DIV	2
 #define EXYNOS4412_FIXED_CIU_CLK_DIV	4
 
+/* Block number in eMMC */
+#define DWMCI_BLOCK_NUM			0xFFFFFFFF
+
+#define SDMMC_EMMCP_BASE		0x1000
+#define SDMMC_MPSECURITY		(SDMMC_EMMCP_BASE + 0x0010)
+#define SDMMC_MPSBEGIN0			(SDMMC_EMMCP_BASE + 0x0200)
+#define SDMMC_MPSEND0			(SDMMC_EMMCP_BASE + 0x0204)
+#define SDMMC_MPSCTRL0			(SDMMC_EMMCP_BASE + 0x020C)
+
+/* SMU control bits */
+#define DWMCI_MPSCTRL_SECURE_READ_BIT		BIT(7)
+#define DWMCI_MPSCTRL_SECURE_WRITE_BIT		BIT(6)
+#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT	BIT(5)
+#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT	BIT(4)
+#define DWMCI_MPSCTRL_USE_FUSE_KEY		BIT(3)
+#define DWMCI_MPSCTRL_ECB_MODE			BIT(2)
+#define DWMCI_MPSCTRL_ENCRYPTION		BIT(1)
+#define DWMCI_MPSCTRL_VALID			BIT(0)
+
 /* Variations in Exynos specific dw-mshc controller */
 enum dw_mci_exynos_type {
 	DW_MCI_TYPE_EXYNOS4210,
@@ -74,6 +93,15 @@  static int dw_mci_exynos_priv_init(struct dw_mci *host)
 {
 	struct dw_mci_exynos_priv_data *priv = host->priv;
 
+	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) {
+		mci_writel(host, MPSBEGIN0, 0);
+		mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
+		mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
+			DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
+			DWMCI_MPSCTRL_VALID |
+			DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
+	}
+
 	return 0;
 }
 
@@ -107,6 +135,7 @@  static int dw_mci_exynos_resume(struct device *dev)
 {
 	struct dw_mci *host = dev_get_drvdata(dev);
 
+	dw_mci_exynos_priv_init(host);
 	return dw_mci_resume(host);
 }