From patchwork Thu Aug 29 11:41:08 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuvaraj CD X-Patchwork-Id: 2851272 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E25899F2F4 for ; Thu, 29 Aug 2013 11:41:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6D57C203F3 for ; Thu, 29 Aug 2013 11:41:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EAF7F203E6 for ; Thu, 29 Aug 2013 11:41:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756064Ab3H2Ll0 (ORCPT ); Thu, 29 Aug 2013 07:41:26 -0400 Received: from mail-pd0-f179.google.com ([209.85.192.179]:50470 "EHLO mail-pd0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756039Ab3H2LlZ (ORCPT ); Thu, 29 Aug 2013 07:41:25 -0400 Received: by mail-pd0-f179.google.com with SMTP id v10so340009pde.38 for ; Thu, 29 Aug 2013 04:41:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=dXdjqsUFgn0LjkGrqbdEBo8FxSPharUbtVTvTY5Z8jo=; b=E59Dcig/zwQka+CbN/nRhVwg11+B01IoRYKnzI/IqnsBOvQPnIjC/NldvQvWN8qa9o TaF5ujE2RNIbOj7vrsG/WRH7ZnlDOsQ/CJCSWz2qX8hZEKteZbhMbVW6QbWOGgSfyWj/ AP9TgH6NuD4kmtObLr8fZK012Zvwj3SmabFdnO2yfk5ETheRskv72hIogo3THkVwFZNt jjaP7nuATcYfGlYdld2+3BrRnCOfktRLF+lGN9YY9gUl5F/AQ0Wq1QeDmu6VdW1X4Np5 LR21srEy2QS9av4k6ubn8RJQ39kTcGxJq4RFudmR4owlBKYafDGFLDJSPEVgwOD1SRaa G5XQ== X-Received: by 10.66.228.38 with SMTP id sf6mr3996004pac.21.1377776484592; Thu, 29 Aug 2013 04:41:24 -0700 (PDT) Received: from yuvaraj-ubuntu.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id iu7sm37454485pbc.45.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 29 Aug 2013 04:41:23 -0700 (PDT) From: Yuvaraj Kumar C D To: linux-samsung-soc@vger.kernel.org, kgene.kim@samsung.com, devicetree@vger.kernel.org Cc: rob.herring@calxeda.com, pawel.moll@arm.com, mark.rutland@arm.com, swarren@wwwdotorg.org, ian.campbell@citrix.com, t.figa@samsung.com, dianders@chromium.org, cjb@laptop.org, thomas.abraham@linaro.org, ks.giri@samsung.com, Yuvaraj Kumar C D Subject: [PATCH V6] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC Date: Thu, 29 Aug 2013 17:11:08 +0530 Message-Id: <1377776468-24808-1-git-send-email-yuvaraj.cd@samsung.com> X-Mailer: git-send-email 1.7.9.5 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the device tree node entries for exynos5420 SOC. Exynos5420 has a different version of DWMMC controller,so a new compatible string is used to distinguish it from the prior SOC's. This patch depends on mmc: dw_mmc: exynos: Add a new compatible string for exynos5420 changes since v5: 1.removed instance index from node name. 2.changed the node name to mshc. 3.changed the reg property value for mshc_2. changes since v4: 1.Droppped the bypass-smu binding property. 2.Used compatible string "samsung,exynos5250-dw-mshc" for controller instance which does not have SMU. changes since V3: 1.change fifo-depth size from 0x80 to 0x40 2.Move the below properties a.card-detect-delay b.samsung,dw-mshc-ciu-div c.samsung,dw-mshc-sdr-timing d.samsung,dw-mshc-ddr-timing from SOC dts to board dts file as suggested by Doug Anderson changes since V2: 1.dropped num-slots property from node as its not required if number of card slots available is 1. 2.Move the below properties a.fifo-depth b.card-detect-delay c.samsung,dw-mshc-ciu-div d.samsung,dw-mshc-sdr-timing e.samsung,dw-mshc-ddr-timing from board dts to SOC dts,as these are not board specific properties. 3.Updated the binding document exynos-dw-mshc.txt. changes since V1: 1.disable node by status = disabled in SOC file 2.enable node by status = okay in board specific file Signed-off-by: Yuvaraj Kumar C D Reviewed-by: Doug Anderson --- .../devicetree/bindings/mmc/exynos-dw-mshc.txt | 2 + arch/arm/boot/dts/exynos5420-smdk5420.dts | 33 +++++++++++++++++ arch/arm/boot/dts/exynos5420.dtsi | 39 ++++++++++++++++++++ 3 files changed, 74 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt index 6d1c098..84cd56f 100644 --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt @@ -16,6 +16,8 @@ Required Properties: specific extensions. - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250 specific extensions. + - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420 + specific extensions. * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface unit (ciu) clock. This property is applicable only for Exynos5 SoC's and diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index bafba25..fe22f97 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -31,6 +31,39 @@ }; }; + mshc@12200000 { + status = "okay"; + broken-cd; + supports-highspeed; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; + }; + + mshc@12220000 { + status = "okay"; + supports-highspeed; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + dp-controller@145B0000 { pinctrl-names = "default"; pinctrl-0 = <&dp_hpd>; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index d537cd7..65375f0 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -22,6 +22,9 @@ compatible = "samsung,exynos5420"; aliases { + mshc0 = &mshc_0; + mshc1 = &mshc_1; + mshc2 = &mshc_2; pinctrl0 = &pinctrl_0; pinctrl1 = &pinctrl_1; pinctrl2 = &pinctrl_2; @@ -84,6 +87,42 @@ clock-names = "mfc"; }; + mshc_0: mshc@12200000 { + compatible = "samsung,exynos5420-dw-mshc"; + interrupts = <0 75 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12200000 0x2000>; + clocks = <&clock 351>, <&clock 132>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + mshc_1: mshc@12210000 { + compatible = "samsung,exynos5420-dw-mshc"; + interrupts = <0 76 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12210000 0x2000>; + clocks = <&clock 352>, <&clock 133>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + mshc_2: mshc@12220000 { + compatible = "samsung,exynos5250-dw-mshc"; + interrupts = <0 77 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12220000 0x1000>; + clocks = <&clock 353>, <&clock 134>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + mct@101C0000 { compatible = "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>;