From patchwork Tue Sep 24 00:21:13 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bresticker X-Patchwork-Id: 2931111 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 17B3BBFF05 for ; Tue, 24 Sep 2013 00:21:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2303020216 for ; Tue, 24 Sep 2013 00:21:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1CB86201DD for ; Tue, 24 Sep 2013 00:21:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753732Ab3IXAVd (ORCPT ); Mon, 23 Sep 2013 20:21:33 -0400 Received: from mail-vb0-f74.google.com ([209.85.212.74]:43920 "EHLO mail-vb0-f74.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753738Ab3IXAVY (ORCPT ); Mon, 23 Sep 2013 20:21:24 -0400 Received: by mail-vb0-f74.google.com with SMTP id w16so448312vbf.3 for ; Mon, 23 Sep 2013 17:21:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CAwfJ0Z/FO9EWWl7CXUh0AfWvV3+/ib81ErdOvxvX2g=; b=gAOmpNoXeraStRo+gDnoo+w/grislT6nk8LD0lUBIkEJv7fFgTkq+nFJdrTI4LjfQb vrrWeWlp1CyDxmIuynNA2iJgGTnnfr17l+wh6X/GWHbA/s5nt4tzaH0cuiNsxAaNfh39 duAXJ38OlQL1FJcYS76TwY2Q2U/YgqWAt2n+mjQk4V/gv4gRvuwbotmd8YtdSk0inwDf OeeL94BYbw2webJdyIO/0TvKRid7I5uWNnyLTYlHrZLhTx01NpX+Mil8vuDOlH8+ziQh SyQf7cmNSXr3DU0DU5qeXoGOtxVBYdP3rz+/ouApZu888N57NYZb9nBQumbsr/j7JphW vSDA== X-Gm-Message-State: ALoCoQlS7VBY0AnWAJmDaK1sU5PlHGWebNdryKjJbTbU8QBo1RXU8sNO4PD+RHQ2AJbGeaXxO/DV7fFbg2gBAOu3zp9v55mYiiIkS7IIJPyN8557ByeM27sdrylma/osrNrtcc/csvb4VyhBlPVbeBn/D8CYvgOUJYXLjOyLNujOfwacmiJwaZjH85Kkm/rqURB/URMTPt0mz5FA1+ryI/UATvLVHPzgSg== X-Received: by 10.236.115.198 with SMTP id e46mr9208825yhh.33.1379982082094; Mon, 23 Sep 2013 17:21:22 -0700 (PDT) Received: from corp2gmr1-2.hot.corp.google.com (corp2gmr1-2.hot.corp.google.com [172.24.189.93]) by gmr-mx.google.com with ESMTPS id d23si3959019yhn.2.1969.12.31.16.00.00 (version=TLSv1.1 cipher=AES128-SHA bits=128/128); Mon, 23 Sep 2013 17:21:22 -0700 (PDT) Received: from abrestic.mtv.corp.google.com (abrestic.mtv.corp.google.com [172.22.72.111]) by corp2gmr1-2.hot.corp.google.com (Postfix) with ESMTP id CFF005A4278; Mon, 23 Sep 2013 17:21:21 -0700 (PDT) Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id 5D158220A1B; Mon, 23 Sep 2013 17:21:21 -0700 (PDT) From: Andrew Bresticker To: linux-samsung-soc@vger.kernel.org, Tomasz Figa , Sylwester Nawrocki Cc: Rob Herring , Pawel Moll , Mark Rutland , Stephen Warren , Ian Campbell , Rob Landley , Kukjin Kim , Russell King , Mike Turquette , Grant Likely , Sachin Kamat , Jiri Kosina , Rahul Sharma , Leela Krishna Amudala , Stephen Boyd , Tushar Behera , Doug Anderson , Padmavathi Venna , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andrew Bresticker Subject: [PATCH V2 1/6] clk: exynos-audss: convert to platform device Date: Mon, 23 Sep 2013 17:21:13 -0700 Message-Id: <1379982078-23381-1-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 1.8.4 In-Reply-To: <1379711637-5226-1-git-send-email-abrestic@chromium.org> References: <1379711637-5226-1-git-send-email-abrestic@chromium.org> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-5.8 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Exynos AudioSS clock controller will later be modified to allow input clocks to be specified via device-tree in order to support multiple Exynos SoCs. This will introduce a dependency on the core SoC clock controller being initialized first so that the AudioSS driver can look up its input clocks, but the order in which clock providers are probed in of_clk_init() is not guaranteed. Since deferred probing is not supported in of_clk_init() and the AudioSS block is not the core controller, we can initialize it later as a platform device. Signed-off-by: Andrew Bresticker --- Changes since v1: - add clk_unregister() calls to remove callback - fixed minor nits from Tomasz --- drivers/clk/samsung/clk-exynos-audss.c | 78 ++++++++++++++++++++++++++++------ 1 file changed, 65 insertions(+), 13 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index 39b40aa..c512efd 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include #include @@ -62,24 +64,29 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = { #endif /* CONFIG_PM_SLEEP */ /* register exynos_audss clocks */ -static void __init exynos_audss_clk_init(struct device_node *np) +static int exynos_audss_clk_probe(struct platform_device *pdev) { - reg_base = of_iomap(np, 0); - if (!reg_base) { - pr_err("%s: failed to map audss registers\n", __func__); - return; + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + reg_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(reg_base)) { + dev_err(&pdev->dev, "failed to map audss registers\n"); + return PTR_ERR(reg_base); } - clk_table = kzalloc(sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS, + clk_table = devm_kzalloc(&pdev->dev, + sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS, GFP_KERNEL); if (!clk_table) { - pr_err("%s: could not allocate clk lookup table\n", __func__); - return; + dev_err(&pdev->dev, "could not allocate clk lookup table\n"); + return -ENOMEM; } clk_data.clks = clk_table; clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS; - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get, + &clk_data); clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss", mout_audss_p, ARRAY_SIZE(mout_audss_p), @@ -128,8 +135,53 @@ static void __init exynos_audss_clk_init(struct device_node *np) #endif pr_info("Exynos: Audss: clock setup completed\n"); + + return 0; +} + +static int exynos_audss_clk_remove(struct platform_device *pdev) +{ + int i; + + for (i = 0; i < EXYNOS_AUDSS_MAX_CLKS; i++) { + if (clk_table[i]) + clk_unregister(clk_table[i]); + } + + of_clk_del_provider(pdev->dev.of_node); + + return 0; } -CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock", - exynos_audss_clk_init); -CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock", - exynos_audss_clk_init); + +static const struct of_device_id exynos_audss_clk_of_match[] = { + { .compatible = "samsung,exynos4210-audss-clock", }, + { .compatible = "samsung,exynos5250-audss-clock", }, + {}, +}; + +static struct platform_driver exynos_audss_clk_driver = { + .driver = { + .name = "exynos-audss-clk", + .owner = THIS_MODULE, + .of_match_table = exynos_audss_clk_of_match, + }, + .probe = exynos_audss_clk_probe, + .remove = exynos_audss_clk_remove, +}; + +static int __init exynos_audss_clk_init(void) +{ + return platform_driver_register(&exynos_audss_clk_driver); +} +core_initcall(exynos_audss_clk_init); + +static void __init exynos_audss_clk_exit(void) +{ + platform_driver_unregister(&exynos_audss_clk_driver); +} +module_exit(exynos_audss_clk_exit); + +MODULE_AUTHOR("Padmavathi Venna "); +MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:exynos-audss-clk");