From patchwork Wed Sep 25 11:22:17 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Majewski X-Patchwork-Id: 2941741 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 53415BFF05 for ; Wed, 25 Sep 2013 11:22:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 03F9F2058A for ; Wed, 25 Sep 2013 11:22:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 26A9A20562 for ; Wed, 25 Sep 2013 11:22:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755326Ab3IYLWi (ORCPT ); Wed, 25 Sep 2013 07:22:38 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:44008 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755153Ab3IYLWf (ORCPT ); Wed, 25 Sep 2013 07:22:35 -0400 Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MTO00G65I997EY0@mailout4.samsung.com>; Wed, 25 Sep 2013 20:22:34 +0900 (KST) X-AuditID: cbfee61a-b7f7a6d00000235f-d0-5242c77a6364 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 19.51.09055.A77C2425; Wed, 25 Sep 2013 20:22:34 +0900 (KST) Received: from mcdsrvbld02.digital.local ([106.116.37.23]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MTO00E88I989I10@mmp2.samsung.com>; Wed, 25 Sep 2013 20:22:34 +0900 (KST) From: Lukasz Majewski To: "Rafael J. Wysocki" , Viresh Kumar Cc: Linux PM list , Lukasz Majewski , Lukasz Majewski , linux-kernel , Bartlomiej Zolnierkiewicz , Tomasz Figa , Myungjoo Ham , Kukjin Kim , Kukjin Kim , linux-samsung-soc@vger.kernel.org Subject: [PATCH 1/2] cpufreq: exynos4x12: Use the common clock framework to set APLL clock rate Date: Wed, 25 Sep 2013 13:22:17 +0200 Message-id: <1380108138-30402-2-git-send-email-l.majewski@samsung.com> X-Mailer: git-send-email 1.7.10 In-reply-to: <1380108138-30402-1-git-send-email-l.majewski@samsung.com> References: <1380108138-30402-1-git-send-email-l.majewski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrILMWRmVeSWpSXmKPExsVy+t9jQd2q405BBjdmqllsnLGe1aJ3wVU2 i/7Hr5kt3jzitnjzcDOjxeVdc9gsPvceYbSYcX4fk8XtxhVAFQt7mSzWz3jNYrHxq4cDj8em VZ1sHneu7WHzWDftLbNH35ZVjB6PFrcwenzeJBfAFsVlk5Kak1mWWqRvl8CVsf7OXqaC9QIV z+8+YmxgPMDbxcjJISFgInHs/HlGCFtM4sK99WxdjFwcQgLTGSWe7zwM5XQxSazrOQNWxSag J/H57lMmEFtEwFdi7ePLjCBFzAILmCWWnNrGCpIQFkiUuLhuClgDi4CqxIV939hAbF4BN4m3 WzaxQKyTl3h6vw8szingLrF8/WqwXiGgmiMX77BMYORdwMiwilE0tSC5oDgpPddQrzgxt7g0 L10vOT93EyM4IJ9J7WBc2WBxiFGAg1GJh1fgqGOQEGtiWXFl7iFGCQ5mJRHe8MVOQUK8KYmV ValF+fFFpTmpxYcYpTlYlMR5D7RaBwoJpCeWpGanphakFsFkmTg4pRoYmVgW6Py87lE+m71E P/CPs/WUVVv2vN9VusCuQvintXDWKndukydtzc6epYvrc6S8jaZ+PH7/1J2Xu233lSp/LVB9 xv5tpmbZRga/l81HuqUnN8xmemCs42N4ZMIih2+LTjcefpj73/b7Tv9W+TNL5zU+1L6y+35/ AW/FmTdn75j8CFKXPWbxSYmlOCPRUIu5qDgRADapT7xEAgAA Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In the exynos4x12_set_apll() function, the APLL frequency is set with direct register manipulation. Such approach is not allowed in the common clock framework. The frequency is changed, but the corresponding clock value is not updated. This causes wrong frequency read from cpufreq's cpuinfo_cur_freq sysfs attribute. Tested at: - Exynos4412 - Trats2 board (linux 3.12-rc1) Signed-off-by: Lukasz Majewski Reviewed-by: Bartlomiej Zolnierkiewicz Reviewed-by: Tomasz Figa --- drivers/cpufreq/exynos4x12-cpufreq.c | 23 ++++------------------- 1 file changed, 4 insertions(+), 19 deletions(-) diff --git a/drivers/cpufreq/exynos4x12-cpufreq.c b/drivers/cpufreq/exynos4x12-cpufreq.c index 08b7477..b2f51c9 100644 --- a/drivers/cpufreq/exynos4x12-cpufreq.c +++ b/drivers/cpufreq/exynos4x12-cpufreq.c @@ -128,9 +128,9 @@ static void exynos4x12_set_clkdiv(unsigned int div_index) static void exynos4x12_set_apll(unsigned int index) { - unsigned int tmp, pdiv; + unsigned int tmp, freq = apll_freq_4x12[index].freq; - /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */ + /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */ clk_set_parent(moutcore, mout_mpll); do { @@ -140,24 +140,9 @@ static void exynos4x12_set_apll(unsigned int index) tmp &= 0x7; } while (tmp != 0x2); - /* 2. Set APLL Lock time */ - pdiv = ((apll_freq_4x12[index].mps >> 8) & 0x3f); + clk_set_rate(mout_apll, freq * 1000); - __raw_writel((pdiv * 250), EXYNOS4_APLL_LOCK); - - /* 3. Change PLL PMS values */ - tmp = __raw_readl(EXYNOS4_APLL_CON0); - tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0)); - tmp |= apll_freq_4x12[index].mps; - __raw_writel(tmp, EXYNOS4_APLL_CON0); - - /* 4. wait_lock_time */ - do { - cpu_relax(); - tmp = __raw_readl(EXYNOS4_APLL_CON0); - } while (!(tmp & (0x1 << EXYNOS4_APLLCON0_LOCKED_SHIFT))); - - /* 5. MUX_CORE_SEL = APLL */ + /* MUX_CORE_SEL = APLL */ clk_set_parent(moutcore, mout_apll); do {